Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in LTE connected mode
- 1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
- 1.5.1.4 VCC current consumption in low power idle mode (low power mode enabled)
- 1.5.1.5 VCC current consumption in active mode (low power mode and PSM disabled)
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General purpose input / output (GPIO)
- 1.12 Reserved pin (RSVD)
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Guidelines for external battery charging circuit
- 2.2.1.7 Guidelines for external charging and power path management circuit
- 2.2.1.8 Guidelines for removing VCC supply
- 2.2.1.9 Additional guidelines for VCC supply circuit design
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interfaces
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.6.1 UART interfaces
- 2.6.1.1 Guidelines for UART circuit design
- Providing 1 UART with the full RS-232 functionality (using the complete V.24 link)
- Providing 1 UART with the TXD, RXD, RTS, CTS, DTR and RI lines only
- Providing 1 UART with the TXD, RXD, RTS and CTS lines only
- Providing 2 UARTs with the TXD, RXD, RTS and CTS lines only
- Providing 1 UART with the TXD and RXD lines only
- Providing 2 UARTs with the TXD and RXD lines only
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 USB interface
- 2.6.3 SPI interfaces
- 2.6.4 SDIO interface
- 2.6.5 DDC (I2C) interface
- 2.6.1 UART interfaces
- 2.7 Audio
- 2.8 General purpose input / output (GPIO)
- 2.9 Reserved pin (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Schematic for SARA-R5 series module integration
- 2.13 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between SARA modules
- B Glossary
- Related documents
- Revision history
- Contact
SARA-R5 series - System integration manual
UBX-19041356 - R03 Product testing Page 106 of 123
Confidential
Appendix
A Migration between SARA modules
A.1 Overview
The u-blox SARA form factor (26.0 x 16.0 mm, 96-pin LGA) includes the following series of modules,
with compatible pin assignments as described in Figure 72, so that the modules can be alternatively
mounted on a single application PCB using exactly the same copper, solder resist and paste mask:
SARA-R41x modules supporting LTE Cat M1, LTE Cat NB1 and 2G radio access technologies
SARA-R42x modules supporting LTE Cat M1, LTE Cat NB2 and 2G radio access technologies
SARA-R5xx modules supporting LTE Cat M1 and LTE Cat NB2 radio access technologies
SARA-N2xx modules supporting LTE Cat NB1 radio access technology
SARA-N3xx modules supporting LTE Cat NB2 radio access technology
SARA-G3xx modules supporting 2G radio access technology
SARA-G4xx modules supporting 2G radio access technology
SARA-U2xx modules supporting 3G and 2G radio access technologies
64 63 61 60 58 57 55 54
22 23 25 26 28 29 31 32
11
10
8
7
5
4
2
1
21
19
18
16
15
13
12
43
44
46
47
49
50
52
53
33
35
36
38
39
41
42
65 66 67 68 69 70
71 72 73 74 75 76
77 78
79 80
81 82
83 84
85 86 87 88 89 90
91 92 93 94 95 96
CTS
RTS
DCD
RI
V_INT
V_BCKP
GND
RSVD
RESET_N
GPIO1
PWR_ON
RXD
TXD
3
20
17
14
9
6
24 27 30
51
48
45
40
37
34
5962 56
GND
GND
DSR
DTR
GND
RSVD
GND
GND
RXD_AUX
TXD_AUX
RSVD
GND
GPIO2
GPIO3
SDA
SCL
GPIO4
GND
GND
GND
SPK_P
MIC_BIAS
MIC_GND
MIC_P
GND
VCC
VCC
RSVD
I2S_TXD
I2S_CLK
SIM_CLK
SIM_IO
VSIM
SIM_DET
VCC
MIC_N
SPK_N
SIM_RST
I2S_RXD
I2S_WA
GND
GND
GND
GND
GND
GND
GND
GND
GND
ANT_DET
ANT
SARA-G3xx
Top view
Pin 65-96: GND
64 63 61 60 58 57 55 54
22 23 25 26 28 29 31 32
11
10
8
7
5
4
2
1
21
19
18
16
15
13
12
43
44
46
47
49
50
52
53
33
35
36
38
39
41
42
65 66 67 68 69 70
71 72 73 74 75 76
77 78
79 80
81 82
83 84
85 86 87 88 89 90
91 92 93 94 95 96
CTS
RTS
DCD
RI
V_INT
V_BCKP
GND
CODEC_CLK
RESET_N
GPIO1
PWR_ON
RXD
TXD
3
20
17
14
9
6
24 27 30
51
48
45
40
37
34
5962 56
GND
GND
DSR
DTR
GND
VUSB_DET
GND
GND
USB_D-
USB_D+
RSVD
GND
GPIO2
GPIO3
SDA
SCL
GPIO4
GND
GND
GND
RSVD
RSVD
RSVD
RSVD
GND
VCC
VCC
RSVD
I2S_TXD
I2S_CLK
SIM_CLK
SIM_IO
VSIM
SIM_DET
VCC
RSVD
RSVD
SIM_RST
I2S_RXD
I2S_WA
GND
GND
GND
GND
GND
GND
GND
GND
GND
ANT_DET
ANT
SARA-U2xx
Top view
Pin 65-96: GND
64 63 61 60 58 57 55 54
22 23 25 26 28 29 31 32
11
10
8
7
5
4
2
1
21
19
18
16
15
13
12
43
44
46
47
49
50
52
53
33
35
36
38
39
41
42
65 66 67 68 69 70
71 72 73 74 75 76
77 78
79 80
81 82
83 84
85 86 87 88 89 90
91 92 93 94 95 96
CTS
RTS
DCD
RI
V_INT
V_BCKP
GND
RXD_AUX
PWR_OFF
GPIO1
PWR_ON
RXD
TXD
3
20
17
14
9
6
24 27 30
51
48
45
40
37
34
5962 56
GND
GND
DSR
DTR
GND
TXD_AUX
GND
VSEL
RXD_FT
TXD_FT
RSVD
GND
GPIO2
GPIO3
SDA
SCL
GPIO4
GND
GND
GND
SPK_P
MIC_BIAS
MIC_GND
MIC_P
GND
VCC
VCC
RSVD
I2S_TXD
I2S_CLK
SIM_CLK
SIM_IO
VSIM
SIM_DET
VCC
MIC_N
SPK_N
SIM_RST
I2S_RXD
I2S_WA
GND
GND
GND
GND
GND
GND
GND
GND
GND
ANT_DET
ANT
SARA-G4xx
Top view
Pin 65-96: GND
64 63 61 60 58 57 55 54
22 23 25 26 28 29 31 32
11
10
8
7
5
4
2
1
21
19
18
16
15
13
12
43
44
46
47
49
50
52
53
33
35
36
38
39
41
42
65 66 67 68 69 70
71 72 73 74 75 76
77 78
79 80
81 82
83 84
85 86 87 88 89 90
91 92 93 94 95 96
CTS
RTS
RSVD
RSVD
V_INT
RSVD
GND
RSVD
RESET_N
GPIO1
RSVD
RXD
TXD
3
20
17
14
9
6
24 27 30
51
48
45
40
37
34
5962 56
GND
GND
RSVD
RSVD
GND
RSVD
GND
GND
RSVD
RSVD
RSVD
GND
RSVD
GPIO2
SDA
SCL
RSVD
GND
GND
GND
RSVD
RSVD
RSVD
RSVD
GND
VCC
VCC
RSVD
RSVD
RSVD
SIM_CLK
SIM_IO
VSIM
RSVD
VCC
RSVD
RSVD
SIM_RST
RSVD
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
ANT_DET
ANT
SARA-N2xx
Top view
Pin 65-96: GND
64 63 61 60 58 57 55 54
22 23 25 26 28 29 31 32
11
10
8
7
5
4
2
1
21
19
18
16
15
13
12
43
44
46
47
49
50
52
53
33
35
36
38
39
41
42
65 66 67 68 69 70
71 72 73 74 75 76
77 78
79 80
81 82
83 84
85 86 87 88 89 90
91 92 93 94 95 96
CTS
RTS
DCD
RI
V_INT
V_BCKP
GND
RXD_AUX
RESET_N
GPIO1
PWR_ON
RXD
TXD
3
20
17
14
9
6
24 27 30
51
48
45
40
37
34
5962 56
GND
GND
DSR
DTR
GND
TXD_AUX
GND
VSEL
RXD_FT
TXD_FT
RSVD
GND
GPIO2
GPIO3
SDA
SCL
GPIO4
GND
GND
GND
RSVD
RSVD
RSVD
RSVD
GND
VCC
VCC
ADC1
RSVD
RSVD
SIM_CLK
SIM_IO
VSIM
GPIO5
VCC
RSVD
RSVD
SIM_RST
RSVD
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
ANT_BT
ANT_DET
ANT
SARA-N3xx
Top view
Pin 65-96: GND
64 63 61 60 58 57 55 54
22 23 25 26 28 29 31 32
11
10
8
7
5
4
2
1
21
19
18
16
15
13
12
43
44
46
47
49
50
52
53
33
35
36
38
39
41
42
65 66 67 68 69 70
71 72 73 74 75 76
77 78
79 80
81 82
83 84
85 86 87 88 89 90
91 92 93 94 95 96
CTS
RTS
DCD
RI
V_INT
RSVD
GND
GPIO6
RESET_N
GPIO1
PWR_ON
RXD
TXD
3
20
17
14
9
6
24 27 30
51
48
45
40
37
34
5962 56
GND
GND
DSR
DTR
GND
VUSB_DET
GND
GND
USB_D-
USB_D+
RSVD
GND
GPIO2
GPIO3
SDA
SCL
GPIO4
GND
GND
GND
SDIO_D2
SDIO_CMD
SDIO_D0
SDIO_D1
GND
VCC
VCC
RSVD
I2S_TXD/SPI_CS
I2S_CLK/SPI_CLK
SIM_CLK
SIM_IO
VSIM
GPIO5
VCC
SDIO_D3
SDIO_CLK
SIM_RST
I2S_RXD/SPI_MISO
I2S_WA/SPI_MOSI
GND
GND
GND
GND
GND
GND
GND
GND
GND
ANT_DET
ANT
SARA-R41x
Top view
Pin 65-96: GND
64 63 61 60 58 57 55 54
22 23 25 26 28 29 31 32
11
10
8
7
5
4
2
1
21
19
18
16
15
13
12
43
44
46
47
49
50
52
53
33
35
36
38
39
41
42
65 66 67 68 69 70
71 72 73 74 75 76
77 78
79 80
81 82
83 84
85 86 87 88 89 90
91 92 93 94 95 96
CTS
RTS
DCD
RI
V_INT
RSVD
GND
GPIO6
RESET_N
GPIO1
PWR_ON
RXD
TXD
3
20
17
14
9
6
24 27 30
51
48
45
40
37
34
5962 56
GND
GND
DSR
DTR
GND
VUSB_DET
GND
GND
USB_D-
USB_D+
ANT_GNSS
GND
GPIO2
GPIO3
SDA
SCL
GPIO4
GND
GND
GND
SDIO_D2
SDIO_CMD
SDIO_D0
SDIO_D1
GND
VCC
VCC
EXT_INT
I2S_TXD
I2S_CLK
SIM_CLK
SIM_IO
VSIM
GPIO5
VCC
SDIO_D3
SDIO_CLK
SIM_RST
I2S_RXD
I2S_WA
GND
GND
GND
GND
GND
GND
GND
GND
GND
ANT_DET
ANT
SARA-R5xx
Top view
Pin 65-96: GND
64 63 61 60 58 57 55 54
22 23 25 26 28 29 31 32
11
10
8
7
5
4
2
1
21
19
18
16
15
13
12
43
44
46
47
49
50
52
53
33
35
36
38
39
41
42
65 66 67 68 69 70
71 72 73 74 75 76
77 78
79 80
81 82
83 84
85 86 87 88 89 90
91 92 93 94 95 96
CTS
RTS
DCD
RI
V_INT
USB_3V3
GND
GPIO6
RSVD
GPIO1
PWR_CTRL
RXD
TXD
3
20
17
14
9
6
24 27 30
51
48
45
40
37
34
5962 56
GND
GND
DSR
DTR
GND
USB_5V0
GND
GND
USB_D-
USB_D+
ANT_GNSS
GND
GPIO2
GPIO3
SDA
SCL
GPIO4
GND
GND
GND
ANT_ON
EXTINT
RSVD
RSVD
GND
VCC
VCC
RSVD
I2S_TXD
I2S_CLK
SIM_CLK
SIM_IO
VSIM
GPIO5
VCC
RSVD
TIMEPULSE
SIM_RST
I2S_RXD
I2S_WA
GND
GND
GND
GND
GND
GND
GND
GND
GND
ANT_DET
ANT
SARA-R42x
Top view
Pin 65-96: GND
Figure 72: SARA-R4, SARA-R5, SARA-N2, SARA-N3, SARA-G3, SARA-G4, and SARA-U2 modules’ layout and pin assignment