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SARA-R4/N4 series-AT Commands Manual
UBX-17003787 - R11
14System features
Page 154 of 308
Parameter Type Description
• 5: apply the setting change defined with <op_code>= 2 / 3 / 4 and triggers the
execution of the digital testing. Digital testing of the pins is possible only after the
execution of the AT+UTEST=10,5 command.
• 6: returns the logic value of pins under testing (both input and output); in the [<bit_
padding>]<pin_seq> parameter use this notation to represent each module pin
with its binary digit:
o 0: "low" logic digital level measured at the module pin
o 1: "high" logic digital level measured at the module pin
[<bit_
padding>]<pin_seq>
Number Sequence of hexadecimal digits containing the pin information and the action to
execute:
• SARA-R4 / SARA-N4 - See the Notes and End User Test Application Note [133] for
detailed number description
14.5.10Notes
• Consider these steps to construct the [<bit_padding>]<pin_seq> sequence:
o Consider the total number of the module's pins available
- SARA-R4 / SARA-N4 - 64 pins
o When a non-testable pin is selected, the command does not return an error result code but the value is
not considered and not applied.
o The status of the n-th pin will be represented by the corresponding n-th bit; see the <op_code>
description for the notation of each mode setting
o Convert each group of four binary digits into its hexadecimal representation
SARA-R4 / SARA-N4
See the End User Test Application Note [133] for the list of pins available for testing.
• An example of the AT commands sequence to test the digital pins is reported in Table 15.
Command Response Description
Configure the formatting of the error result code by
means of +CMEE AT command
AT+COPS=2 OK Deregister the module from the network
AT+UTEST=1 OK The module enters the test mode
AT+UTEST=10,2,"000007F400
C000D83F00"
OK The command puts the module in Interface initialised
state; the command saves the pins status to restore it
at the end of the test.
Pins enabled for testing: DSR, RI, DCD, DTR, RTS, CTS,
GPIO1, GPIO2, GPIO3, GPIO4, I2S1_RXD/GPIO6, I2S1_TXD/
GPIO7, GPIO5, I2S1_CLK/GPIO8, I2S1_WA/GPIO9, SPI_
SCLK/GPIO10, SPI_MOSI/GPIO11, SPI_MISO/GPIO12, SPI_
SRDY/GPIO13, SPI_MRDY/GPIO14
AT+UTEST=10,3,"0000049400
4000C01800"
OK Pins configuration:
o DTR, RTS, GPIO3, GPIO4, I2S1_RXD/GPIO6, GPIO5,
I2S1_CLK/GPIO8, SPI_MOSI/GPIO11, SPI_MRDY/
GPIO14 as input
o DSR, RI, DCD, CTS, GPIO1, GPIO2, I2S1_TXD/
GPIO7, I2S1_WA/GPIO9, SPI_SCLK/GPIO10, SPI_
MISO/GPIO12, SPI_SRDY/GPIO13 as output
AT+UTEST=10,4,"0000036000
8000182700"
OK Digital logic value of the output pins:
o DSR, RI, DCD, CTS, GPIO1, GPIO2, I2S1_TXD/
GPIO7, I2S1_WA/GPIO9, SPI_SCLK/GPIO10, SPI_
MISO/GPIO12, SPI_SRDY/GPIO13 set to "high".
AT+UTEST=10,5 OK Configurations made by AT+UTEST=10,2; AT+UTEST=
10,3 and AT+UTEST=10,4 are executed.
AT+UTEST=10,6 000007F400C000D83F00
OK
Logic digital value measured at modules pins:
o DSR, RI, DCD, DTR, RTS, CTS, GPIO1, GPIO2, GPIO3,
GPIO4, I2S1_RXD/GPIO6, I2S1_TXD/GPIO7, GPIO5,
I2S1_CLK/GPIO8, I2S1_WA/GPIO9, SPI_SCLK/GPIO10
, SPI_MOSI/GPIO11, SPI_MISO/GPIO12, SPI_SRDY/
GPIO13, SPI_MRDY/GPIO14: "high" level detected