Integration Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC or 3.3Vaux)
- 1.5.1.1 VCC or 3.3Vaux supply requirements
- 1.5.1.2 VCC or 3.3Vaux current consumption in 2G connected-mode
- 1.5.1.3 VCC or 3.3Vaux current consumption in 3G connected mode
- 1.5.1.4 VCC or 3.3Vaux current consumption in LTE connected-mode
- 1.5.1.5 VCC or 3.3Vaux current consumption in cyclic idle/active mode (power saving enabled)
- 1.5.1.6 VCC or 3.3Vaux current consumption in fixed active-mode (power saving disabled)
- 1.5.2 RTC supply input/output (V_BCKP)
- 1.5.3 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC or 3.3Vaux)
- 1.6 System function interfaces
- 1.7 Antenna interface
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General Purpose Input/Output
- 1.12 Mini PCIe specific signals (W_DISABLE#, LED_WWAN#)
- 1.13 Reserved pins (RSVD)
- 1.14 Not connected pins (NC)
- 1.15 System features
- 1.15.1 Network indication
- 1.15.2 Antenna supervisor
- 1.15.3 Jamming detection
- 1.15.4 IP modes of operation
- 1.15.5 Dual stack IPv4/IPv6
- 1.15.6 TCP/IP and UDP/IP
- 1.15.7 FTP
- 1.15.8 HTTP
- 1.15.9 SSL / TLS
- 1.15.10 Bearer Independent Protocol
- 1.15.11 Wi-Fi integration
- 1.15.12 Firmware update Over AT (FOAT)
- 1.15.13 Firmware update Over The Air (FOTA)
- 1.15.14 Smart temperature management
- 1.15.15 SIM Access Profile (SAP)
- 1.15.16 Power saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC or 3.3Vaux)
- 2.2.1.1 General guidelines for VCC or 3.3Vaux supply circuit selection and design
- 2.2.1.2 Guidelines for VCC or 3.3Vaux supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC or 3.3Vaux supply circuit design using a Low Drop-Out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable Li-Ion or Li-Pol battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery
- 2.2.1.6 Additional guidelines for VCC or 3.3Vaux supply circuit design
- 2.2.1.7 Guidelines for external battery charging circuit
- 2.2.1.8 Guidelines for external battery charging and power path management circuit
- 2.2.1.9 Guidelines for VCC or 3.3Vaux supply layout design
- 2.2.1.10 Guidelines for grounding layout design
- 2.2.2 RTC supply output (V_BCKP)
- 2.2.3 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC or 3.3Vaux)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.7 Audio interface
- 2.8 General Purpose Input/Output
- 2.9 Mini PCIe specific signals (W_DISABLE#, LED_WWAN#)
- 2.10 Reserved pins (RSVD)
- 2.11 Module placement
- 2.12 TOBY-L2 series module footprint and paste mask
- 2.13 MPCI-L2 series module installation
- 2.14 Thermal guidelines
- 2.15 ESD guidelines
- 2.16 Schematic for TOBY-L2 and MPCI-L2 series module integration
- 2.17 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 4.1 Product certification approval overview
- 4.2 US Federal Communications Commission notice
- 4.3 Innovation, Science and Economic Development Canada notice
- 4.4 Brazilian Anatel certification
- 4.5 European Conformance CE mark
- 4.6 Australian Regulatory Compliance Mark
- 4.7 Taiwanese NCC certification
- 4.8 Japanese Giteki certification
- 5 Product testing
- Appendix
- A Migration between TOBY-L1 and TOBY-L2
- B Glossary
- Related documents
- Revision history
- Contact
TOBY-L2 and MPCI-L2 series - System Integration Manual
UBX-13004618 - R26 Design-in
Page 87 of 162
2.3.2 Module reset (RESET_N or PERST#)
2.3.2.1 Guidelines for RESET_N and PERST# circuit design
The TOBY-L2 series RESET_N is equipped with an internal pull-up to the VCC supply and the MPCI-L2 series
PERST# is equipped with an internal pull-up to the 3.3 V rail, as described in Figure 43. An external pull-up resistor
is not required and should not be provided.
If connecting the RESET_N or PERST# input to a push button, the pin will be externally accessible on the
application device. According to EMC/ESD requirements of the application, an additional ESD protection device
(e.g. the EPCOS CA05P4S14THSG varistor) should be provided close to accessible point on the line connected to
this pin, as described in Figure 43 and Table 30.
ESD sensitivity rating of the RESET_N and PERST# pins is 1 kV (HBM according to JESD22-A114). Higher
protection level can be required if the line is externally accessible on the application board, e.g. if an
accessible push button is directly connected to the RESET_N or PERST# pin, and it can be achieved by
mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor) close to accessible point.
An open drain output is suitable to drive the RESET_N and PERST# inputs from an application processor as they
are equipped with an internal pull-up to VCC supply and to the 3.3 V rail respectively, as described in Figure 43.
A compatible push-pull output of an application processor can also be used. In any case, take care to set the
proper level in all the possible scenarios to avoid an inappropriate module reset, switch-on or switch-off.
TOBY-L2 series
VCC
23
RESET_N
Power-on
push button
ESD
Open
Drain
Output
Application
Processor
TOBY-L2 series
VCC
23
RESET_N
TP
TP
50 k
50 k
MPCI-L2 series
22
PERST#
Power-on
push button
ESD
Open
Drain
Output
Application
Processor
MPCI-L2 series
22
PERST#
45 k 45 k
3V3
3V3
Figure 43: RESET_N and PERST# application circuits using a push button and an open drain output of an application processor
Reference
Description
Remarks
ESD
Varistor for ESD protection
CT0402S14AHSG - EPCOS
Table 30: Example of ESD protection component for the RESET_N and PERST# application circuits
If the external reset function is not required by the customer application, the RESET_N input pin can be left
unconnected to external components, but it is recommended providing direct access on the application
board by means of an accessible test point directly connected to the RESET_N pin.