Integration Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC or 3.3Vaux)
- 1.5.1.1 VCC or 3.3Vaux supply requirements
- 1.5.1.2 VCC or 3.3Vaux current consumption in 2G connected-mode
- 1.5.1.3 VCC or 3.3Vaux current consumption in 3G connected mode
- 1.5.1.4 VCC or 3.3Vaux current consumption in LTE connected-mode
- 1.5.1.5 VCC or 3.3Vaux current consumption in cyclic idle/active mode (power saving enabled)
- 1.5.1.6 VCC or 3.3Vaux current consumption in fixed active-mode (power saving disabled)
- 1.5.2 RTC supply input/output (V_BCKP)
- 1.5.3 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC or 3.3Vaux)
- 1.6 System function interfaces
- 1.7 Antenna interface
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General Purpose Input/Output
- 1.12 Mini PCIe specific signals (W_DISABLE#, LED_WWAN#)
- 1.13 Reserved pins (RSVD)
- 1.14 Not connected pins (NC)
- 1.15 System features
- 1.15.1 Network indication
- 1.15.2 Antenna supervisor
- 1.15.3 Jamming detection
- 1.15.4 IP modes of operation
- 1.15.5 Dual stack IPv4/IPv6
- 1.15.6 TCP/IP and UDP/IP
- 1.15.7 FTP
- 1.15.8 HTTP
- 1.15.9 SSL / TLS
- 1.15.10 Bearer Independent Protocol
- 1.15.11 Wi-Fi integration
- 1.15.12 Firmware update Over AT (FOAT)
- 1.15.13 Firmware update Over The Air (FOTA)
- 1.15.14 Smart temperature management
- 1.15.15 SIM Access Profile (SAP)
- 1.15.16 Power saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC or 3.3Vaux)
- 2.2.1.1 General guidelines for VCC or 3.3Vaux supply circuit selection and design
- 2.2.1.2 Guidelines for VCC or 3.3Vaux supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC or 3.3Vaux supply circuit design using a Low Drop-Out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable Li-Ion or Li-Pol battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery
- 2.2.1.6 Additional guidelines for VCC or 3.3Vaux supply circuit design
- 2.2.1.7 Guidelines for external battery charging circuit
- 2.2.1.8 Guidelines for external battery charging and power path management circuit
- 2.2.1.9 Guidelines for VCC or 3.3Vaux supply layout design
- 2.2.1.10 Guidelines for grounding layout design
- 2.2.2 RTC supply output (V_BCKP)
- 2.2.3 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC or 3.3Vaux)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.7 Audio interface
- 2.8 General Purpose Input/Output
- 2.9 Mini PCIe specific signals (W_DISABLE#, LED_WWAN#)
- 2.10 Reserved pins (RSVD)
- 2.11 Module placement
- 2.12 TOBY-L2 series module footprint and paste mask
- 2.13 MPCI-L2 series module installation
- 2.14 Thermal guidelines
- 2.15 ESD guidelines
- 2.16 Schematic for TOBY-L2 and MPCI-L2 series module integration
- 2.17 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 4.1 Product certification approval overview
- 4.2 US Federal Communications Commission notice
- 4.3 Innovation, Science and Economic Development Canada notice
- 4.4 Brazilian Anatel certification
- 4.5 European Conformance CE mark
- 4.6 Australian Regulatory Compliance Mark
- 4.7 Taiwanese NCC certification
- 4.8 Japanese Giteki certification
- 5 Product testing
- Appendix
- A Migration between TOBY-L1 and TOBY-L2
- B Glossary
- Related documents
- Revision history
- Contact
TOBY-L2 and MPCI-L2 series - System Integration Manual
UBX-13004618 - R26 System description
Page 49 of 162
DSR signal behavior
If AT&S1 is set, as it is by default, the DSR module output line is set by default to the OFF state (high level) at UART
initialization. The DSR line is then set to the OFF state when the module is in command mode
14
or in online
command mode
14
and is set to the ON state when the module is in data mode
14
.
If AT&S0 is set, the DSR module output line is set by default to the ON state (low level) at UART initialization and
is then always held in the ON state.
DTR signal behavior
The DTR module input line is set by default to the OFF state (high level) at UART initialization. The module then
holds the DTR line in the OFF state if the line is not activated by the DTE: an active pull-up is enabled inside the
module on the DTR input.
Module behavior according to DTR status can be changed by AT command configuration (for more details see the
u-blox AT Commands Manual [3], &D AT command description).
If AT+UPSV=3 is set, the DTR line is monitored by the module to manage the power saving configuration (for
more details, see section 1.9.2.4 and u-blox AT Commands Manual [3], AT+UPSV):
When an OFF-to-ON transition occurs on the DTR input, the UART is enabled and the module is forced to
active-mode; after ~5 ms from the transition, the switch is completed and data can be received without loss.
The module cannot enter low power idle-mode and the UART is keep enabled as long as the DTR input line
is held in the ON state
If the DTR input line is set to the OFF state by the DTE, the UART is disabled (held in low power mode) and
the module automatically enters low power idle-mode whenever possible
DCD signal behavior
If AT&C1 is set, as it is by default, the DCD module output line is set by default to the OFF state (high level) at
UART initialization. The module then sets the DCD line according to the carrier detect status: ON if the carrier is
detected, OFF otherwise.
In case of voice calls, DCD is set to the ON state when the call is established.
If a Packet Switched Data call occurs before activating the PPP protocol (data mode), a dial-up application must
provide the ATD*99***<context_number># to the module: with this command the module switches from
command mode
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to data mode
14
and can accept PPP packets. The module sets the DCD line to the ON state, then
answers with a CONNECT to confirm the ATD*99 command. The DCD ON is not related to the context activation
but with the data mode.
The DCD is set to ON during the execution of the +CMGS, +CMGW, +USOWR, +USODL AT commands
requiring input data from the DTE: the DCD line is set to the ON state as soon as the switch to binary/text
input mode is completed and the prompt is issued; DCD line is set to OFF as soon as the input mode is
interrupted or completed (for more details see the u-blox AT Commands Manual [3]).
The DCD line is kept in the ON state, even during the online command mode
14
, to indicate that the data
call is still established even if suspended, while if the module enters command mode
14
, the DSR line is set
to the OFF state. For more details see DSR signal behavior description.
For scenarios when the DCD line setting is requested for different reasons (e.g. SMS texting during online
command mode
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), the DCD line changes to guarantee the correct behavior for all the scenarios. For
example, in case of SMS texting in online command mode
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, if the data call is released, DCD is kept ON till
the SMS command execution is completed (even if the data call release would request DCD set OFF).
If AT&C0 is set, the DCD module output line is set by default to the ON state (low level) at UART initialization and
is then always held in the ON state.
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For the definition of the interface data mode, command mode and online command mode see the u-blox AT Commands Manual [3]