Integration Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC or 3.3Vaux)
- 1.5.1.1 VCC or 3.3Vaux supply requirements
- 1.5.1.2 VCC or 3.3Vaux current consumption in 2G connected-mode
- 1.5.1.3 VCC or 3.3Vaux current consumption in 3G connected mode
- 1.5.1.4 VCC or 3.3Vaux current consumption in LTE connected-mode
- 1.5.1.5 VCC or 3.3Vaux current consumption in cyclic idle/active mode (power saving enabled)
- 1.5.1.6 VCC or 3.3Vaux current consumption in fixed active-mode (power saving disabled)
- 1.5.2 RTC supply input/output (V_BCKP)
- 1.5.3 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC or 3.3Vaux)
- 1.6 System function interfaces
- 1.7 Antenna interface
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General Purpose Input/Output
- 1.12 Mini PCIe specific signals (W_DISABLE#, LED_WWAN#)
- 1.13 Reserved pins (RSVD)
- 1.14 Not connected pins (NC)
- 1.15 System features
- 1.15.1 Network indication
- 1.15.2 Antenna supervisor
- 1.15.3 Jamming detection
- 1.15.4 IP modes of operation
- 1.15.5 Dual stack IPv4/IPv6
- 1.15.6 TCP/IP and UDP/IP
- 1.15.7 FTP
- 1.15.8 HTTP
- 1.15.9 SSL / TLS
- 1.15.10 Bearer Independent Protocol
- 1.15.11 Wi-Fi integration
- 1.15.12 Firmware update Over AT (FOAT)
- 1.15.13 Firmware update Over The Air (FOTA)
- 1.15.14 Smart temperature management
- 1.15.15 SIM Access Profile (SAP)
- 1.15.16 Power saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC or 3.3Vaux)
- 2.2.1.1 General guidelines for VCC or 3.3Vaux supply circuit selection and design
- 2.2.1.2 Guidelines for VCC or 3.3Vaux supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC or 3.3Vaux supply circuit design using a Low Drop-Out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable Li-Ion or Li-Pol battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery
- 2.2.1.6 Additional guidelines for VCC or 3.3Vaux supply circuit design
- 2.2.1.7 Guidelines for external battery charging circuit
- 2.2.1.8 Guidelines for external battery charging and power path management circuit
- 2.2.1.9 Guidelines for VCC or 3.3Vaux supply layout design
- 2.2.1.10 Guidelines for grounding layout design
- 2.2.2 RTC supply output (V_BCKP)
- 2.2.3 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC or 3.3Vaux)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.7 Audio interface
- 2.8 General Purpose Input/Output
- 2.9 Mini PCIe specific signals (W_DISABLE#, LED_WWAN#)
- 2.10 Reserved pins (RSVD)
- 2.11 Module placement
- 2.12 TOBY-L2 series module footprint and paste mask
- 2.13 MPCI-L2 series module installation
- 2.14 Thermal guidelines
- 2.15 ESD guidelines
- 2.16 Schematic for TOBY-L2 and MPCI-L2 series module integration
- 2.17 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 4.1 Product certification approval overview
- 4.2 US Federal Communications Commission notice
- 4.3 Innovation, Science and Economic Development Canada notice
- 4.4 Brazilian Anatel certification
- 4.5 European Conformance CE mark
- 4.6 Australian Regulatory Compliance Mark
- 4.7 Taiwanese NCC certification
- 4.8 Japanese Giteki certification
- 5 Product testing
- Appendix
- A Migration between TOBY-L1 and TOBY-L2
- B Glossary
- Related documents
- Revision history
- Contact
TOBY-L2 and MPCI-L2 series - System Integration Manual
UBX-13004618 - R26 System description
Page 13 of 162
1.2.1 Internal blocks
As described in Figure 2, each MPCI-L2 series module integrates one TOBY-L2 series module, which consists of the
following internal sections: RF, baseband and power management.
RF section
The RF section is composed of RF transceiver, PAs, LNAs, crystal oscillator, filters, duplexers and RF switches.
Tx signal is pre-amplified by RF transceiver, then output to the primary antenna input/output port (ANT1) of the
module via power amplifier (PA), SAW band pass filters band, specific duplexer and antenna switch.
Dual receiving paths are implemented according to LTE Down-Link MIMO 2 x 2 and 3G Receiver Diversity radio
technologies supported by the modules as LTE category 4 and HSDPA category 24 User Equipments: incoming
signals are received through the primary (ANT1) and the secondary (ANT2) antenna input ports which are
connected to the RF transceiver via specific antenna switch, diplexer, duplexer, LNA, SAW band pass filters.
RF transceiver performs modulation, up-conversion of the baseband I/Q signals for Tx, down-conversion and
demodulation of the dual RF signals for Rx. The RF transceiver contains:
Automatically gain controlled direct conversion Zero-IF receiver,
Highly linear RF demodulator / modulator capable GMSK, 8-PSK, QPSK, 16-QAM, 64-QAM,
Fractional-N Sigma-Delta RF synthesizer,
VCO.
Power Amplifiers (PA) amplify the Tx signal modulated by the RF transceiver
RF switches connect primary (ANT1) and secondary (ANT2) antenna ports to the suitable Tx / Rx path
Low Noise Amplifiers (LNA) enhance the received sensitivity
SAW duplexers separate the Tx and Rx signal paths and provide RF filtering
SAW band pass filters enhance the rejection of out-of-band signals
26 MHz crystal oscillator generates the clock reference in active-mode or connected-mode.
Baseband and power management section
The Baseband and Power Management section is composed of the following main elements:
A mixed signal ASIC, which integrates
Microprocessor for control functions
DSP core for LTE/3G/2G Layer 1 and digital processing of Rx and Tx signal paths
Memory interface controller
Dedicated peripheral blocks for control of the USB, SIM and GPIO digital interfaces
Analog front end interfaces to RF transceiver ASIC
Memory system, which includes NAND flash and LPDDR
Voltage regulators to derive all the subsystem supply voltages from the module supply input VCC
Voltage sources for external use: V_BCKP and V_INT (not available on MPCI-L2 series modules)
Hardware power on
Hardware reset
Low power idle-mode support
32.768 kHz crystal oscillator to provide the clock reference in the low power idle-mode, which can be set by
enable power saving configuration using the AT+UPSV command.