Integration Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC or 3.3Vaux)
- 1.5.1.1 VCC or 3.3Vaux supply requirements
- 1.5.1.2 VCC or 3.3Vaux current consumption in 2G connected-mode
- 1.5.1.3 VCC or 3.3Vaux current consumption in 3G connected mode
- 1.5.1.4 VCC or 3.3Vaux current consumption in LTE connected-mode
- 1.5.1.5 VCC or 3.3Vaux current consumption in cyclic idle/active mode (power saving enabled)
- 1.5.1.6 VCC or 3.3Vaux current consumption in fixed active-mode (power saving disabled)
- 1.5.2 RTC supply input/output (V_BCKP)
- 1.5.3 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC or 3.3Vaux)
- 1.6 System function interfaces
- 1.7 Antenna interface
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General Purpose Input/Output
- 1.12 Mini PCIe specific signals (W_DISABLE#, LED_WWAN#)
- 1.13 Reserved pins (RSVD)
- 1.14 Not connected pins (NC)
- 1.15 System features
- 1.15.1 Network indication
- 1.15.2 Antenna supervisor
- 1.15.3 Jamming detection
- 1.15.4 IP modes of operation
- 1.15.5 Dual stack IPv4/IPv6
- 1.15.6 TCP/IP and UDP/IP
- 1.15.7 FTP
- 1.15.8 HTTP
- 1.15.9 SSL / TLS
- 1.15.10 Bearer Independent Protocol
- 1.15.11 Wi-Fi integration
- 1.15.12 Firmware update Over AT (FOAT)
- 1.15.13 Firmware update Over The Air (FOTA)
- 1.15.14 Smart temperature management
- 1.15.15 SIM Access Profile (SAP)
- 1.15.16 Power saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC or 3.3Vaux)
- 2.2.1.1 General guidelines for VCC or 3.3Vaux supply circuit selection and design
- 2.2.1.2 Guidelines for VCC or 3.3Vaux supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC or 3.3Vaux supply circuit design using a Low Drop-Out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable Li-Ion or Li-Pol battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery
- 2.2.1.6 Additional guidelines for VCC or 3.3Vaux supply circuit design
- 2.2.1.7 Guidelines for external battery charging circuit
- 2.2.1.8 Guidelines for external battery charging and power path management circuit
- 2.2.1.9 Guidelines for VCC or 3.3Vaux supply layout design
- 2.2.1.10 Guidelines for grounding layout design
- 2.2.2 RTC supply output (V_BCKP)
- 2.2.3 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC or 3.3Vaux)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.7 Audio interface
- 2.8 General Purpose Input/Output
- 2.9 Mini PCIe specific signals (W_DISABLE#, LED_WWAN#)
- 2.10 Reserved pins (RSVD)
- 2.11 Module placement
- 2.12 TOBY-L2 series module footprint and paste mask
- 2.13 MPCI-L2 series module installation
- 2.14 Thermal guidelines
- 2.15 ESD guidelines
- 2.16 Schematic for TOBY-L2 and MPCI-L2 series module integration
- 2.17 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 4.1 Product certification approval overview
- 4.2 US Federal Communications Commission notice
- 4.3 Innovation, Science and Economic Development Canada notice
- 4.4 Brazilian Anatel certification
- 4.5 European Conformance CE mark
- 4.6 Australian Regulatory Compliance Mark
- 4.7 Taiwanese NCC certification
- 4.8 Japanese Giteki certification
- 5 Product testing
- Appendix
- A Migration between TOBY-L1 and TOBY-L2
- B Glossary
- Related documents
- Revision history
- Contact
TOBY-L2 and MPCI-L2 series - System Integration Manual
UBX-13004618 - R26 Design-in
Page 129 of 162
The antenna interface application circuit implemented in the EMC / ESD approved reference designs of TOBY-L2
and MPCI-L2 series modules is described in Figure 48 in case of antennas detection circuit not implemented, and
is described in Figure 49 and Table 35 in case of antennas detection circuit implemented (section 2.4).
RESET_N and PERST# pin
The following precautions are suggested for the RESET_N and the PERST# line of TOBY-L2 and MPCI-L2 series
modules, depending on the application board handling, to satisfy ESD immunity test requirements:
It is recommended to keep the connection line to RESET_N and PERST# as short as possible
Maximum ESD sensitivity rating of the RESET_N and the PERST# pin is 1 kV (Human Body Model according to
JESD22-A114). Higher protection level could be required if the RESET_N or PERST# pin is externally accessible on
the application board. The following precautions are suggested to achieve higher protection level:
A general purpose ESD protection device (e.g. EPCOS CA05P4S14THSG varistor array or EPCOS
CT0402S14AHSG varistor) should be mounted on the RESET_N or PERST# line, close to accessible point
The RESET_N and PERST# application circuit implemented in the EMC / ESD approved reference designs of
TOBY-L2 and MPCI-L2 series modules is described in Figure 43 and Table 30 (section 2.3.2).
SIM interface
The following precautions are suggested for TOBY-L2 and MPCI-L2 series modules SIM interface, depending on
the application board handling, to satisfy ESD immunity test requirements:
A bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) must be mounted on the lines
connected to the SIM interface pins to assure SIM interface functionality when an electrostatic discharge is
applied to the application board enclosure
It is suggested to use as short as possible connection lines at SIM pins
Maximum ESD sensitivity rating of SIM interface pins is 1 kV (Human Body Model according to JESD22-A114).
Higher protection level could be required if SIM interface pins are externally accessible on the application board.
The following precautions are suggested to achieve higher protection level:
A low capacitance (i.e. less than 10 pF) ESD protection device (e.g. Tyco Electronics PESD0402-140) should be
mounted on each SIM interface line, close to accessible points (i.e. close to the SIM card holder)
The SIM interface application circuit implemented in the EMC / ESD approved reference designs of TOBY-L2 and
MPCI-L2 series modules is described in Figure 50 and Table 36 (section 2.5).
Other pins and interfaces
All the module pins that are externally accessible on the device integrating TOBY-L2 and MPCI-L2 series module
should be included in the ESD immunity test since they are considered to be a port as defined in ETSI EN 301 489-
1 [19]. Depending on applicability, to satisfy ESD immunity test requirements according to ESD category level, all
the module pins that are externally accessible should be protected up to ±4 kV for direct Contact Discharge and
up to ±8 kV for Air Discharge applied to the enclosure surface.
The maximum ESD sensitivity rating of all the other pins of the module is 1 kV (Human Body Model according to
JESD22-A114). Higher protection level could be required if the relative pin is externally accessible on the application
board. The following precautions are suggested to achieve higher protection level:
USB interface: a very low capacitance (i.e. less or equal to 1 pF) ESD protection device (e.g. Tyco Electronics
PESD0402-140 ESD protection device) should be mounted on the USB_D+ and USB_D- lines, close to the
accessible points (i.e. close to the USB connector)
Other pins: a general purpose ESD protection device (e.g. EPCOS CA05P4S14THSG varistor array or EPCOS
CT0402S14AHSG varistor) should be mounted on the related line, close to accessible point