Integration Manual

TOBY-L2 and MPCI-L2 series - System Integration Manual
UBX-13004618 - R26 Design-in
Page 117 of 162
Reference
Description
Part Number – Manufacturer
C11, C12, C13, C14
10 nF Capacitor Ceramic X5R 0402 10% 50V
GRM155R71C103KA88 – Murata
D1, D2
Low Capacitance ESD Protection
USB0002RP or USB0002DP – AVX
EMI1, EMI2, EMI3,
EMI4
Chip Ferrite Bead Noise/EMI Suppression Filter
1800 Ohm at 100 MHz, 2700 Ohm at 1 GHz
BLM15HD182SN1 – Murata
J1
Microphone Connector
Various manufacturers
J2
Speaker Connector
Various manufacturers
MIC
2.2 k Electret Microphone
Various manufacturers
R1, R2
4.7 k Resistor 0402 5% 0.1 W
RC0402JR-074K7L - Yageo Phycomp
R3
10 k Resistor 0402 5% 0.1 W
RC0402JR-0710KL - Yageo Phycomp
R4, R5
2.2 k Resistor 0402 5% 0.1 W
RC0402JR-072K2L – Yageo Phycomp
SPK
32  Speaker
Various manufacturers
U1
16-Bit Mono Audio Voice Codec
MAX9860ETG+ - Maxim
Table 45: Example of components for audio voice codec application circuit
Do not apply voltage to any I
2
S pin before the switch-on of I
2
S supply source (V_INT), to avoid latch-up of
circuits and allow a proper boot of the module. If the external signals connected to the cellular module
cannot be tri-stated or set low, insert a multi channel digital switch (e.g. TI SN74CB3Q16244, TS5A3159,
or TS5A63157) between the two-circuit connections and set to high impedance before V_INT switch-on.
ESD sensitivity rating of I
2
S interface pins is 1 kV (Human Body Model according to JESD22-A114). Higher
protection level could be required if the lines are externally accessible and it can be achieved by mounting
a general purpose ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to accessible points.
If the I
2
S digital audio pins are not used, they can be left unconnected on the application board.
2.7.1.2 Guidelines for digital audio layout design
I
2
S interface and clock output lines require the same consideration regarding electro-magnetic interference as any
other high speed digital interface. Keep the traces short and avoid coupling with RF lines / parts or sensitive analog
inputs, since the signals can cause the radiation of some harmonics of the digital data frequency.
2.7.1.3 Guidelines for analog audio layout design
Accurate design of the analog audio circuit is very important to obtain clear and high quality audio. The GSM
signal burst has a repetition rate of 217 Hz that lies in the audible range. A careful layout is required to reduce the
risk of noise from audio lines due to both VCC burst noise coupling and RF detection.
General guidelines for the uplink path (microphone), which is commonly the most sensitive, are the following:
 Avoid coupling of any noisy signal to microphone lines: it is strongly recommended to route microphone lines
away from module VCC supply line, any switching regulator line, RF antenna lines, digital lines and any other
possible noise source.
 Avoid coupling between microphone and speaker / receiver lines.
 Optimize the mechanical design of the application device, the position, orientation and mechanical fixing (for
example, using rubber gaskets) of microphone and speaker parts in order to avoid echo interference between
uplink path and downlink path.
 Keep ground separation from microphone lines to other noisy signals. Use an intermediate ground layer or
vias wall for coplanar signals.
 In case of external audio device providing differential microphone input, route microphone signal lines as a
differential pair embedded in ground to reduce differential noise pick-up. The balanced configuration will help
reject the common mode noise.