Integration Manual

TOBY-L2 and MPCI-L2 series - System Integration Manual
UBX-13004618 - R04 Advance Information System description
Page 11 of 141
1.2.1 Internal blocks
As described in Figure 2, each MPCI-L2 series module integrates one TOBY-L2 series module, which consists of
the following internal sections: RF, baseband and power management.
RF section
The RF section is composed of RF transceiver, PAs, LNAs, crystal oscillator, filters, duplexers and RF switches.
Tx signal is pre-amplified by RF transceiver, then output to the primary antenna input/output port (ANT1) of the
module via power amplifier (PA), SAW band pass filters band, specific duplexer and antenna switch.
Dual receiving paths are implemented according to LTE Down-Link MIMO 2 x 2 and 3G Receiver Diversity radio
technologies supported by the modules as LTE category 4 and HSDPA category 24 User Equipments: incoming
signals are received through the primary (ANT1) and the secondary (ANT2) antenna input ports which are
connected to the RF transceiver via specific antenna switch, diplexer, duplexer, LNA, SAW band pass filters.
 RF transceiver performs modulation, up-conversion of the baseband I/Q signals for Tx, down-conversion and
demodulation of the dual RF signals for Rx. The RF transceiver contains:
Automatically gain controlled direct conversion Zero-IF receiver,
Highly linear RF demodulator / modulator capable GMSK, 8-PSK, QPSK, 16-QAM, 64-QAM,
Fractional-N Sigma-Delta RF synthesizer,
VCO.
 Power Amplifiers (PA) amplify the Tx signal modulated by the RF transceiver
 RF switches connect primary (ANT1) and secondary (ANT2) antenna ports to the suitable Tx / Rx path
 Low Noise Amplifiers (LNA) enhance the received sensitivity
 SAW duplexers separate the Tx and Rx signal paths and provide RF filtering
 SAW band pass filters enhance the rejection of out-of-band signals
 26 MHz crystal oscillator generates the clock reference in active-mode or connected-mode.
Baseband and power management section
The Baseband and Power Management section is composed of the following main elements:
 A mixed signal ASIC, which integrates
Microprocessor for control functions
DSP core for LTE/3G/2G Layer 1 and digital processing of Rx and Tx signal paths
Memory interface controller
Dedicated peripheral blocks for control of the USB, SIM and GPIO digital interfaces
Analog front end interfaces to RF transceiver ASIC
 Memory system, which includes NAND flash and LPDDR
 Voltage regulators to derive all the subsystem supply voltages from the module supply input VCC
 Voltage sources for external use: V_BCKP and V_INT (not available on MPCI-L2 series modules)
 Hardware power on
 Hardware reset
 Low power idle-mode support
 32.768 kHz crystal oscillator to provide the clock reference in the low power idle-mode, which can be set by
enable power saving configuration using the AT+UPSV command.