Integration Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC or 3.3Vaux)
- 1.5.1.1 VCC or 3.3Vaux supply requirements
- 1.5.1.2 VCC or 3.3Vaux current consumption in 2G connected-mode
- 1.5.1.3 VCC or 3.3Vaux current consumption in 3G connected mode
- 1.5.1.4 VCC or 3.3Vaux current consumption in LTE connected-mode
- 1.5.1.5 VCC or 3.3Vaux current consumption in cyclic idle/active mode (power saving enabled)
- 1.5.1.6 VCC or 3.3Vaux current consumption in fixed active-mode (power saving disabled)
- 1.5.2 RTC supply input/output (V_BCKP)
- 1.5.3 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC or 3.3Vaux)
- 1.6 System function interfaces
- 1.7 Antenna interface
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General Purpose Input/Output
- 1.12 Mini PCIe specific signals (W_DISABLE#, LED_WWAN#)
- 1.13 Reserved pins (RSVD)
- 1.14 Not connected pins (NC)
- 1.15 System features
- 1.15.1 Network indication
- 1.15.2 Antenna supervisor
- 1.15.3 Jamming detection
- 1.15.4 IP modes of operation
- 1.15.5 Dual stack IPv4/IPv6
- 1.15.6 TCP/IP and UDP/IP
- 1.15.7 FTP
- 1.15.8 HTTP
- 1.15.9 SSL / TLS
- 1.15.10 Bearer Independent Protocol
- 1.15.11 Wi-Fi integration
- 1.15.12 Firmware update Over AT (FOAT)
- 1.15.13 Firmware update Over The Air (FOTA)
- 1.15.14 Smart temperature management
- 1.15.15 SIM Access Profile (SAP)
- 1.15.16 Power saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC or 3.3Vaux)
- 2.2.1.1 General guidelines for VCC or 3.3Vaux supply circuit selection and design
- 2.2.1.2 Guidelines for VCC or 3.3Vaux supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC or 3.3Vaux supply circuit design using a Low Drop-Out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable Li-Ion or Li-Pol battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery
- 2.2.1.6 Additional guidelines for VCC or 3.3Vaux supply circuit design
- 2.2.1.7 Guidelines for external battery charging circuit
- 2.2.1.8 Guidelines for external battery charging and power path management circuit
- 2.2.1.9 Guidelines for VCC or 3.3Vaux supply layout design
- 2.2.1.10 Guidelines for grounding layout design
- 2.2.2 RTC supply output (V_BCKP)
- 2.2.3 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC or 3.3Vaux)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.7 Audio interface
- 2.8 General Purpose Input/Output
- 2.9 Mini PCIe specific signals (W_DISABLE#, LED_WWAN#)
- 2.10 Reserved pins (RSVD)
- 2.11 Module placement
- 2.12 TOBY-L2 series module footprint and paste mask
- 2.13 MPCI-L2 series module installation
- 2.14 Thermal guidelines
- 2.15 ESD guidelines
- 2.16 Schematic for TOBY-L2 and MPCI-L2 series module integration
- 2.17 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 4.1 Product certification approval overview
- 4.2 US Federal Communications Commission notice
- 4.3 Innovation, Science and Economic Development Canada notice
- 4.4 Brazilian Anatel certification
- 4.5 European Conformance CE mark
- 4.6 Australian Regulatory Compliance Mark
- 4.7 Taiwanese NCC certification
- 4.8 Japanese Giteki certification
- 5 Product testing
- Appendix
- A Migration between TOBY-L1 and TOBY-L2
- B Glossary
- Related documents
- Revision history
- Contact
TOBY-L2 and MPCI-L2 series - System Integration Manual
UBX-13004618 - R26 Design-in
Page 98 of 162
The DC impedance at RF port for some antennas may be a DC open (e.g. linear monopole) or a DC short to
reference GND (e.g. PIFA antenna). For those antennas, without the diagnostic circuit of Figure 49, the measured
DC resistance is always at the limits of the measurement range (respectively open or short), and there is no means
to distinguish between a defect on antenna path with similar characteristics (respectively: removal of linear antenna
or RF cable shorted to GND for PIFA antenna).
Furthermore, any other DC signal injected to the RF connection from ANT connector to radiating element will alter
the measurement and produce invalid results for antenna detection.
It is recommended to use an antenna with a built-in diagnostic resistor in the range from 5 k to 30 k to
assure good antenna detection functionality and avoid a reduction of module RF performance. The choke
inductor should exhibit a parallel Self Resonance Frequency (SRF) in the range of 1 GHz to improve the RF
isolation of load resistor.
For example:
Consider an antenna with built-in DC load resistor of 15 k. Using the +UANTR AT command, the module reports
the resistance value evaluated from the antenna connector provided on the application board to GND:
Reported values close to the used diagnostic resistor nominal value (i.e. values from 13 k to 17 k if a 15 k
diagnostic resistor is used) indicate that the antenna is properly connected.
Values close to the measurement range maximum limit (approximately 50 k) or an open-circuit “over range”
report (see u-blox AT Commands Manual [3]) means that that the antenna is not connected or the RF cable is
broken.
Reported values below the measurement range minimum limit (1 k) highlights a short to GND at antenna or
along the RF cable.
Measurement inside the valid measurement range and outside the expected range may indicate an improper
connection, damaged antenna or wrong value of antenna load resistor for diagnostic.
Reported value could differ from the real resistance value of the diagnostic resistor mounted inside the antenna
assembly due to antenna cable length, antenna cable capacity and the used measurement method.
If the primary / secondary antenna detection function is not required by the customer application, the
ANT_DET pin can be left not connected and the ANT1 / ANT2 pins can be directly connected to the related
antenna connector by means of a 50 transmission line as described in Figure 48.
2.4.2.2 Guidelines for ANT_DET layout design
The recommended layout for the primary antenna detection circuit to be provided on the application board to
achieve the primary antenna detection functionality, implementing the recommended schematic described in
Figure 49 and Table 35, is explained here:
The ANT1 / ANT2 pins have to be connected to the antenna connector by means of a 50 transmission line,
implementing the design guidelines described in section 2.4.1 and the recommendations of the SMA
connector manufacturer.
DC blocking capacitor at ANT1 / ANT2 pins (C2, C3) has to be placed in series to the 50 RF line.
The ANT_DET pin has to be connected to the 50 transmission line by means of a sense line.
Choke inductors in series at the ANT_DET pin (L1, L2) have to be placed so that one pad is on the 50
transmission line and the other pad represents the start of the sense line to the ANT_DET pin.
The additional components (R1, C1 and D1) on the ANT_DET line have to be placed as ESD protection.