Integration Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC or 3.3Vaux)
- 1.5.1.1 VCC or 3.3Vaux supply requirements
- 1.5.1.2 VCC or 3.3Vaux current consumption in 2G connected-mode
- 1.5.1.3 VCC or 3.3Vaux current consumption in 3G connected mode
- 1.5.1.4 VCC or 3.3Vaux current consumption in LTE connected-mode
- 1.5.1.5 VCC or 3.3Vaux current consumption in cyclic idle/active mode (power saving enabled)
- 1.5.1.6 VCC or 3.3Vaux current consumption in fixed active-mode (power saving disabled)
- 1.5.2 RTC supply input/output (V_BCKP)
- 1.5.3 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC or 3.3Vaux)
- 1.6 System function interfaces
- 1.7 Antenna interface
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General Purpose Input/Output
- 1.12 Mini PCIe specific signals (W_DISABLE#, LED_WWAN#)
- 1.13 Reserved pins (RSVD)
- 1.14 Not connected pins (NC)
- 1.15 System features
- 1.15.1 Network indication
- 1.15.2 Antenna supervisor
- 1.15.3 Jamming detection
- 1.15.4 IP modes of operation
- 1.15.5 Dual stack IPv4/IPv6
- 1.15.6 TCP/IP and UDP/IP
- 1.15.7 FTP
- 1.15.8 HTTP
- 1.15.9 SSL / TLS
- 1.15.10 Bearer Independent Protocol
- 1.15.11 Wi-Fi integration
- 1.15.12 Firmware update Over AT (FOAT)
- 1.15.13 Firmware update Over The Air (FOTA)
- 1.15.14 Smart temperature management
- 1.15.15 SIM Access Profile (SAP)
- 1.15.16 Power saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC or 3.3Vaux)
- 2.2.1.1 General guidelines for VCC or 3.3Vaux supply circuit selection and design
- 2.2.1.2 Guidelines for VCC or 3.3Vaux supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC or 3.3Vaux supply circuit design using a Low Drop-Out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable Li-Ion or Li-Pol battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery
- 2.2.1.6 Additional guidelines for VCC or 3.3Vaux supply circuit design
- 2.2.1.7 Guidelines for external battery charging circuit
- 2.2.1.8 Guidelines for external battery charging and power path management circuit
- 2.2.1.9 Guidelines for VCC or 3.3Vaux supply layout design
- 2.2.1.10 Guidelines for grounding layout design
- 2.2.2 RTC supply output (V_BCKP)
- 2.2.3 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC or 3.3Vaux)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.7 Audio interface
- 2.8 General Purpose Input/Output
- 2.9 Mini PCIe specific signals (W_DISABLE#, LED_WWAN#)
- 2.10 Reserved pins (RSVD)
- 2.11 Module placement
- 2.12 TOBY-L2 series module footprint and paste mask
- 2.13 MPCI-L2 series module installation
- 2.14 Thermal guidelines
- 2.15 ESD guidelines
- 2.16 Schematic for TOBY-L2 and MPCI-L2 series module integration
- 2.17 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 4.1 Product certification approval overview
- 4.2 US Federal Communications Commission notice
- 4.3 Innovation, Science and Economic Development Canada notice
- 4.4 Brazilian Anatel certification
- 4.5 European Conformance CE mark
- 4.6 Australian Regulatory Compliance Mark
- 4.7 Taiwanese NCC certification
- 4.8 Japanese Giteki certification
- 5 Product testing
- Appendix
- A Migration between TOBY-L1 and TOBY-L2
- B Glossary
- Related documents
- Revision history
- Contact
TOBY-L2 and MPCI-L2 series - System Integration Manual
UBX-13004618 - R26 System description
Page 57 of 162
1.10 Audio
1.10.1 Digital audio over I
2
S interface
I
2
S digital audio interface is not available on MPCI-L2 modules.
I
2
S digital audio interface is not supported by TOBY-L2 modules ’00‘, ’01‘, ’60‘, ‘L201-02’, ‘L220-62’ vers.
TOBY-L2 series modules include a 4-wire I
2
S digital audio interface (I2S_TXD data output, I2S_RXD data input,
I2S_CLK clock output, I2S_WA world alignment / synchronization signal output) that can be configured by AT
command for digital audio communication with external digital audio devices as an audio codec (for more details
see the u-blox AT Commands Manual [3], +UI2S AT command).
The I
2
S interface can be set to two modes, by the <I2S_mode> parameter of the AT+UI2S command:
PCM mode (short synchronization signal): I
2
S word alignment signal is set high for 1 or 2 clock cycles for the
synchronization, and then is set low for 31 or 30 clock cycles according to the 32 clock cycles frame length.
Normal I
2
S mode (long synchronization signal): I
2
S word alignment is set high / low with a 50% duty cycle
(high for 16 clock cycles / low for 16 clock cycles, according to the 32 clock cycles frame length).
The modules support I
2
S master role only: I2S_CLK clock and I2S_WA world alignment / synchronization signal
are generated by the module.
The sample rate of transmitted/received words, which corresponds to the I
2
S word alignment / synchronization
signal frequency, can be set by the <I2S_sample_rate> parameter of AT+UI2S to:
8 kHz
16 kHz
The modules support I
2
S transmit and I
2
S receive data 16-bit words long, linear, mono. Data is transmitted and
read in 2’s complement notation. MSB is transmitted and read first.
I
2
S clock signal frequency is set to 32 x <I2S_sample_rate>: the frame length, which corresponds to the I
2
S word
alignment / synchronization signal period, is 32 I
2
S clock cycles long.
For the complete description of the possible configurations and settings of the I
2
S digital audio interface for
PCM and Normal I
2
S modes refer to the u-blox AT Commands Manual [3], +UI2S AT command.
The internal audio processing system is summarized in Figure 26: external digital audio devices can be interfaced
directly to the digital signal processing part via the I
2
S digital interface. Audio processing can be controlled by AT
commands: see Audio Interface and Audio Parameters Tuning sections in the u-blox AT Commands Manual [3].
ECHFP
To
Radio TX
From
Radio RX
RES
NS
DRCLPF EQAGC
I2S_RXD
I2S_TXD
Volume &
Mute
CNG
AGCEQ
LPF
DRC
NSHPF
Volume &
Mute
PCM
Player
Tone
Generator
Legend:
EC = Echo Cancellation
RES = Residual Echo Suppression
NS = Noise Suppression
LPF = Low Pass Filter
HPF = High Pass Filter
EQU = Equalizer
AGC = Additional Gain Control
DRC = Dynamic Range
Compression
CNG = Comfort Noise Generator
TOBY-L2
Figure 26: TOBY-L2 modules internal audio processing system block diagram
The internal audio processing system of TOBY-L2 modules does not support the side-tone.