Integration Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC or 3.3Vaux)
- 1.5.1.1 VCC or 3.3Vaux supply requirements
- 1.5.1.2 VCC or 3.3Vaux current consumption in 2G connected-mode
- 1.5.1.3 VCC or 3.3Vaux current consumption in 3G connected mode
- 1.5.1.4 VCC or 3.3Vaux current consumption in LTE connected-mode
- 1.5.1.5 VCC or 3.3Vaux current consumption in cyclic idle/active mode (power saving enabled)
- 1.5.1.6 VCC or 3.3Vaux current consumption in fixed active-mode (power saving disabled)
- 1.5.2 RTC supply input/output (V_BCKP)
- 1.5.3 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC or 3.3Vaux)
- 1.6 System function interfaces
- 1.7 Antenna interface
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General Purpose Input/Output
- 1.12 Mini PCIe specific signals (W_DISABLE#, LED_WWAN#)
- 1.13 Reserved pins (RSVD)
- 1.14 Not connected pins (NC)
- 1.15 System features
- 1.15.1 Network indication
- 1.15.2 Antenna supervisor
- 1.15.3 Jamming detection
- 1.15.4 IP modes of operation
- 1.15.5 Dual stack IPv4/IPv6
- 1.15.6 TCP/IP and UDP/IP
- 1.15.7 FTP
- 1.15.8 HTTP
- 1.15.9 SSL / TLS
- 1.15.10 Bearer Independent Protocol
- 1.15.11 Wi-Fi integration
- 1.15.12 Firmware update Over AT (FOAT)
- 1.15.13 Firmware update Over The Air (FOTA)
- 1.15.14 Smart temperature management
- 1.15.15 SIM Access Profile (SAP)
- 1.15.16 Power saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC or 3.3Vaux)
- 2.2.1.1 General guidelines for VCC or 3.3Vaux supply circuit selection and design
- 2.2.1.2 Guidelines for VCC or 3.3Vaux supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC or 3.3Vaux supply circuit design using a Low Drop-Out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable Li-Ion or Li-Pol battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery
- 2.2.1.6 Additional guidelines for VCC or 3.3Vaux supply circuit design
- 2.2.1.7 Guidelines for external battery charging circuit
- 2.2.1.8 Guidelines for external battery charging and power path management circuit
- 2.2.1.9 Guidelines for VCC or 3.3Vaux supply layout design
- 2.2.1.10 Guidelines for grounding layout design
- 2.2.2 RTC supply output (V_BCKP)
- 2.2.3 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC or 3.3Vaux)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.7 Audio interface
- 2.8 General Purpose Input/Output
- 2.9 Mini PCIe specific signals (W_DISABLE#, LED_WWAN#)
- 2.10 Reserved pins (RSVD)
- 2.11 Module placement
- 2.12 TOBY-L2 series module footprint and paste mask
- 2.13 MPCI-L2 series module installation
- 2.14 Thermal guidelines
- 2.15 ESD guidelines
- 2.16 Schematic for TOBY-L2 and MPCI-L2 series module integration
- 2.17 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 4.1 Product certification approval overview
- 4.2 US Federal Communications Commission notice
- 4.3 Innovation, Science and Economic Development Canada notice
- 4.4 Brazilian Anatel certification
- 4.5 European Conformance CE mark
- 4.6 Australian Regulatory Compliance Mark
- 4.7 Taiwanese NCC certification
- 4.8 Japanese Giteki certification
- 5 Product testing
- Appendix
- A Migration between TOBY-L1 and TOBY-L2
- B Glossary
- Related documents
- Revision history
- Contact
TOBY-L2 and MPCI-L2 series - System Integration Manual
UBX-13004618 - R26 System description
Page 48 of 162
CTS signal behavior
The module hardware flow control output (CTS line) is set to the ON state (low level) at UART initialization.
If the hardware flow control is enabled, as it is by default, the CTS line indicates when the UART interface is
enabled (data can be received): the module drives the CTS line to the ON state or to the OFF state when it is either
able or not able to accept data from the DTE over the UART (for example see section 1.9.2.4, Figure 23).
The module guarantees the reception of characters when the CTS line is set to the ON state, and the module
is also able to accept up to 3 characters after the CTS line is set to the OFF state.
If hardware flow control is enabled, then when the CTS line is OFF it does not necessarily mean that the
module is in low power idle-mode, but only that the UART is not enabled, as the module could be forced
to stay in active-mode for other activities, e.g. related to the network or related to other interfaces.
If hardware flow control is enabled and the multiplexer protocol is active, then the CTS line state is mapped
to FCon / FCoff MUX command for flow control matters outside the power saving configuration while the
physical CTS line is still used as a UART power state indicator (see the Mux Implementation Application
Note [12]).
The CTS hardware flow control setting can be changed by AT commands (for more details, see the u-blox AT
Commands Manual [3], AT&K, AT\Q, AT+IFC AT commands).
If the hardware flow control is not enabled, the CTS line still indicates when the UART interface is enabled, as it
does when hardware flow control is enabled. The module drives the CTS line to the ON state or to the OFF state
when it is either able or not able to accept data from the DTE over the UART interface.
When the power saving configuration is enabled by AT+UPSV command and the hardware flow-control is
not implemented in the DTE/DCE connection, data sent by the DTE can be lost: the first character sent when
the module is in low power idle-mode will not be a valid communication character (see section 1.9.2.4 and
in particular the sub-section “Wake up via data reception” for further details).
RTS signal behavior
The hardware flow control input (RTS line) is set by default to the OFF state (high level) at UART initialization. The
module then holds the RTS line in the OFF state if the line is not activated by the DTE: an active pull-up is enabled
inside the module on the RTS input.
If the HW flow control is enabled, as it is by default, the module monitors the RTS line to detect permission from
the DTE to send data to the DTE itself. If the RTS line is set to the OFF state, any on-going data transmission from
the module is interrupted until the RTS line changes to the ON state.
The DTE must still be able to accept a certain number of characters after the RTS line is set to the OFF state:
the module guarantees the transmission interruption within two characters from RTS state change.
The module behavior according to the RTS hardware flow control status can be configured by AT commands (for
more details, see the u-blox AT Commands Manual [3], AT&K, AT\Q, AT+IFC AT commands).
If AT+UPSV=2 is set and HW flow control is disabled, the module monitors the RTS line to manage the power
saving configuration (for more details, see section 1.9.2.4 and u-blox AT Commands Manual [3], AT+UPSV):
When an OFF-to-ON transition occurs on the RTS input, the UART is enabled and the module is forced to
active-mode; after ~5 ms from the transition the switch is completed and data can be received without loss.
The module cannot enter low power idle-mode and the UART is keep enabled as long as the RTS input line is
held in the ON state
If the RTS input line is set to the OFF state by the DTE, the UART is disabled (held in low power mode) and the
module automatically enters low power idle-mode whenever possible