Integration Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC or 3.3Vaux)
- 1.5.1.1 VCC or 3.3Vaux supply requirements
- 1.5.1.2 VCC or 3.3Vaux current consumption in 2G connected-mode
- 1.5.1.3 VCC or 3.3Vaux current consumption in 3G connected mode
- 1.5.1.4 VCC or 3.3Vaux current consumption in LTE connected-mode
- 1.5.1.5 VCC or 3.3Vaux current consumption in cyclic idle/active mode (power saving enabled)
- 1.5.1.6 VCC or 3.3Vaux current consumption in fixed active-mode (power saving disabled)
- 1.5.2 RTC supply input/output (V_BCKP)
- 1.5.3 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC or 3.3Vaux)
- 1.6 System function interfaces
- 1.7 Antenna interface
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General Purpose Input/Output
- 1.12 Mini PCIe specific signals (W_DISABLE#, LED_WWAN#)
- 1.13 Reserved pins (RSVD)
- 1.14 Not connected pins (NC)
- 1.15 System features
- 1.15.1 Network indication
- 1.15.2 Antenna supervisor
- 1.15.3 Jamming detection
- 1.15.4 IP modes of operation
- 1.15.5 Dual stack IPv4/IPv6
- 1.15.6 TCP/IP and UDP/IP
- 1.15.7 FTP
- 1.15.8 HTTP
- 1.15.9 SSL / TLS
- 1.15.10 Bearer Independent Protocol
- 1.15.11 Wi-Fi integration
- 1.15.12 Firmware update Over AT (FOAT)
- 1.15.13 Firmware update Over The Air (FOTA)
- 1.15.14 Smart temperature management
- 1.15.15 SIM Access Profile (SAP)
- 1.15.16 Power saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC or 3.3Vaux)
- 2.2.1.1 General guidelines for VCC or 3.3Vaux supply circuit selection and design
- 2.2.1.2 Guidelines for VCC or 3.3Vaux supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC or 3.3Vaux supply circuit design using a Low Drop-Out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable Li-Ion or Li-Pol battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery
- 2.2.1.6 Additional guidelines for VCC or 3.3Vaux supply circuit design
- 2.2.1.7 Guidelines for external battery charging circuit
- 2.2.1.8 Guidelines for external battery charging and power path management circuit
- 2.2.1.9 Guidelines for VCC or 3.3Vaux supply layout design
- 2.2.1.10 Guidelines for grounding layout design
- 2.2.2 RTC supply output (V_BCKP)
- 2.2.3 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC or 3.3Vaux)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.7 Audio interface
- 2.8 General Purpose Input/Output
- 2.9 Mini PCIe specific signals (W_DISABLE#, LED_WWAN#)
- 2.10 Reserved pins (RSVD)
- 2.11 Module placement
- 2.12 TOBY-L2 series module footprint and paste mask
- 2.13 MPCI-L2 series module installation
- 2.14 Thermal guidelines
- 2.15 ESD guidelines
- 2.16 Schematic for TOBY-L2 and MPCI-L2 series module integration
- 2.17 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 4.1 Product certification approval overview
- 4.2 US Federal Communications Commission notice
- 4.3 Innovation, Science and Economic Development Canada notice
- 4.4 Brazilian Anatel certification
- 4.5 European Conformance CE mark
- 4.6 Australian Regulatory Compliance Mark
- 4.7 Taiwanese NCC certification
- 4.8 Japanese Giteki certification
- 5 Product testing
- Appendix
- A Migration between TOBY-L1 and TOBY-L2
- B Glossary
- Related documents
- Revision history
- Contact
TOBY-L2 and MPCI-L2 series - System Integration Manual
UBX-13004618 - R26 Design-in
Page 116 of 162
Figure 64 and Table 45 describe an application circuit for the I
2
S digital audio interface providing basic voice
capability using an external audio voice codec, in particular the Maxim MAX9860 audio codec.
DAC and ADC integrated in the external audio codec respectively converts an incoming digital data stream to
analog audio output through a mono amplifier and converts the microphone input signal to the digital bit
stream over the digital audio interface,
A digital side-tone mixer integrated in the external audio codec provides loopback of the microphones/ADC
signal to the DAC/headphone output.
The module’s I
2
S interface (I
2
S master) is connected to the related pins of the external audio codec (I
2
S slave).
The GPIO6 of the TOBY-L2 series module (that provides a suitable digital output clock) is connected to the
clock input of the external audio codec to provide clock reference.
The external audio codec is controlled by the TOBY-L2 series module using the DDC (I
2
C) interface, which can
concurrently communicate with other I
2
C devices and control an external audio codec.
The V_INT output supplies the external audio codec, defining proper digital interfaces voltage level.
Additional components are provided for EMC and ESD immunity conformity: a 10 nF bypass capacitor and a
series chip ferrite bead noise/EMI suppression filter provided on each microphone line input and speaker line
output of the external codec as described in Figure 64 and Table 45. The necessity of these or other additional
parts for EMC improvement may depend on the specific application board design.
Specific AT commands are available to configure the Maxim MAX9860 audio codec: for more details see the u-blox
AT Commands Manual [3], +UVGC, +UEXTDCONF AT commands.
As various external audio codecs other than the one described in Figure 64 / Table 45 can be used to provide voice
capability, the appropriate specific application circuit has to be implemented and configured according to the
particular external digital audio device or audio codec used and according to the application requirements.
TOBY-L2 series
except the product versions
‘00’,‘01’,‘60’,‘L201-02’,’L220-62’
R2R1
BCLK
GND
U1
LRCLK
Audio
Codec
SDIN
SDOUT
SDA
SCL
MCLK
IRQn
R3
C3C2
C1
VDD
1V8
MICBIAS
C4
R4
C5
C6
MICLN
MICLP
D1
Microphone
Connector
MIC
C12 C11
J1
MICGND
R5
C8 C7
D2
SPK
Speaker
Connector
OUTP
OUTN
J2
C10 C9C14 C13
EMI3
EMI4
EMI1
EMI2
GPIO6
55
SDA
54
SCL
61
GND
5
V_INT
52
I2S_CLK
50
I2S_WA
51
I2S_TXD
53
I2S_RXD
Figure 64: I
2
S interface application circuit with an external audio codec to provide voice capability
Reference
Description
Part Number – Manufacturer
C1
100 nF Capacitor Ceramic X5R 0402 10% 10V
GRM155R71C104KA01 – Murata
C2, C4, C5, C6
1 µF Capacitor Ceramic X5R 0402 10% 6.3 V
GRM155R60J105KE19 – Murata
C3
10 µF Capacitor Ceramic X5R 0603 20% 6.3 V
GRM188R60J106ME47 – Murata
C7, C8, C9, C10
27 pF Capacitor Ceramic COG 0402 5% 25 V
GRM1555C1H270JZ01 – Murata