Integration Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC or 3.3Vaux)
- 1.5.1.1 VCC or 3.3Vaux supply requirements
- 1.5.1.2 VCC or 3.3Vaux current consumption in 2G connected-mode
- 1.5.1.3 VCC or 3.3Vaux current consumption in 3G connected mode
- 1.5.1.4 VCC or 3.3Vaux current consumption in LTE connected-mode
- 1.5.1.5 VCC or 3.3Vaux current consumption in cyclic idle/active mode (power saving enabled)
- 1.5.1.6 VCC or 3.3Vaux current consumption in fixed active-mode (power saving disabled)
- 1.5.2 RTC supply input/output (V_BCKP)
- 1.5.3 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC or 3.3Vaux)
- 1.6 System function interfaces
- 1.7 Antenna interface
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General Purpose Input/Output
- 1.12 Mini PCIe specific signals (W_DISABLE#, LED_WWAN#)
- 1.13 Reserved pins (RSVD)
- 1.14 Not connected pins (NC)
- 1.15 System features
- 1.15.1 Network indication
- 1.15.2 Antenna supervisor
- 1.15.3 Jamming detection
- 1.15.4 IP modes of operation
- 1.15.5 Dual stack IPv4/IPv6
- 1.15.6 TCP/IP and UDP/IP
- 1.15.7 FTP
- 1.15.8 HTTP
- 1.15.9 SSL / TLS
- 1.15.10 Bearer Independent Protocol
- 1.15.11 Wi-Fi integration
- 1.15.12 Firmware update Over AT (FOAT)
- 1.15.13 Firmware update Over The Air (FOTA)
- 1.15.14 Smart temperature management
- 1.15.15 SIM Access Profile (SAP)
- 1.15.16 Power saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC or 3.3Vaux)
- 2.2.1.1 General guidelines for VCC or 3.3Vaux supply circuit selection and design
- 2.2.1.2 Guidelines for VCC or 3.3Vaux supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC or 3.3Vaux supply circuit design using a Low Drop-Out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable Li-Ion or Li-Pol battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery
- 2.2.1.6 Additional guidelines for VCC or 3.3Vaux supply circuit design
- 2.2.1.7 Guidelines for external battery charging circuit
- 2.2.1.8 Guidelines for external battery charging and power path management circuit
- 2.2.1.9 Guidelines for VCC or 3.3Vaux supply layout design
- 2.2.1.10 Guidelines for grounding layout design
- 2.2.2 RTC supply output (V_BCKP)
- 2.2.3 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC or 3.3Vaux)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.7 Audio interface
- 2.8 General Purpose Input/Output
- 2.9 Mini PCIe specific signals (W_DISABLE#, LED_WWAN#)
- 2.10 Reserved pins (RSVD)
- 2.11 Module placement
- 2.12 TOBY-L2 series module footprint and paste mask
- 2.13 MPCI-L2 series module installation
- 2.14 Thermal guidelines
- 2.15 ESD guidelines
- 2.16 Schematic for TOBY-L2 and MPCI-L2 series module integration
- 2.17 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 4.1 Product certification approval overview
- 4.2 US Federal Communications Commission notice
- 4.3 Innovation, Science and Economic Development Canada notice
- 4.4 Brazilian Anatel certification
- 4.5 European Conformance CE mark
- 4.6 Australian Regulatory Compliance Mark
- 4.7 Taiwanese NCC certification
- 4.8 Japanese Giteki certification
- 5 Product testing
- Appendix
- A Migration between TOBY-L1 and TOBY-L2
- B Glossary
- Related documents
- Revision history
- Contact
TOBY-L2 and MPCI-L2 series - System Integration Manual
UBX-13004618 - R26 Design-in
Page 114 of 162
R2
LDO regulator
ELLA-W131
Wi-Fi module
3V3VCC
U1
C1
R1
Wi-Fi enable
SD_D0
15
SD_D1
16
SD_D2
11
SD_D3
12
SD_CLK
14
SD_CMD
13
PDn
9
OUTIN
SENSE
BYP
SHDNn
GND
TOBY-L2 series
cellular module
(except ‘00’, ’01’, ’60’ versions)
SDIO_D0
66
SDIO_D1
68
SDIO_D2
63
SDIO_D3
67
SDIO_CLK
64
SDIO_CMD
65
V_INT
5
GPIO1
21
C3
3V3
4
C5
LDO regulator 1V8VCC
U2
C2
OUTIN
SENSE
BYP
SHDNn
GND
C4
VIO
5
C6
1V8
6
R3
R4
R5
R6
R7
RESETn
10
SLEEP_CLK
19
CFG
20
LED_0
2
R9
GND
ANT1
29
ANT2
26
R8
DL1
GND
Band-Pass filter
L1
Wi-Fi
antenna
FL1
Figure 63: Application circuit for connecting a TOBY-L2 cellular module to a u-blox ELLA-W131 Wi-Fi module
Reference
Description
Part Number - Manufacturer
C1, C2
1 µF Capacitor Ceramic X7R 0603 10% 25 V
GRM188R71E105KA12 - Murata
C3, C4
10 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C103KA01 - Murata
C5, C6
10 µF Capacitor Ceramic X5R 0603 20% 6.3 V
GRM188R60J106ME47 - Murata
DL1
LED Green SMT 0603
LTST-C190KGKT - Lite-on Technology Corporation
FL1
Wi-Fi 2.4 GHz band-pass filter with LTE B7 coexistence
B39242B9604P810 - TDK EPCOS
L1
15 nH Multilayer Inductor 0603 3% 0.25 A
MLG0603P15NHT000 - TDK
R1
470 k Resistor 0402 5% 0.1 W
RK73B1ETTD474J - KOA
R2, R3, R4, R5, R6, R7
22 Resistor 0402 5% 0.1 W
RK73B1ETTP220J - KOA
R8
470 Resistor 0402 5% 0.1 W
RK73B1ETTP471J - KOA
R9
47 k Resistor 0402 5% 0.1 W
RK73B1ETTD473J - KOA
U1
LDO Linear Regulator 3.0 V 0.3 A
LT1962EMS8-3.3 - Linear Technology
U2
LDO Linear Regulator 1.8 V 0.3 A
LT1962EMS8-1.8 - Linear Technology
Table 44: Components for connecting TOBY-L2xx-50S cellular modules to u-blox ELLA-W1 series Wi-Fi modules
Do not apply voltage to any SDIO interface pin before the switch-on of SDIO interface supply source (V_INT),
to avoid latch-up of circuits and allow a proper boot of the module.
ESD sensitivity rating of SDIO interface pins is 1 kV (HMB according to JESD22-A114). Higher protection
level could be required if the lines are externally accessible and it can be achieved by mounting a very low
capacitance ESD protection (e.g. Tyco Electronics PESD0402-140 ESD), close to accessible points.
If the SDIO interface pins are not used, they can be left unconnected on the application board.
2.6.4.2 Guidelines for SDIO layout design
The SDIO serial interface requires the same consideration regarding electro-magnetic interference as any other
high speed digital interface.
Keep the traces short, avoid stubs and avoid coupling with RF lines / parts or sensitive analog inputs, since the
signals can cause the radiation of some harmonics of the digital data frequency.
Consider the usage of low value series damping resistors (see the application circuit in Figure 63 / Table 44) to
avoid reflections and other losses in signal integrity, which may create ringing and loss of a square wave shape.