Integration Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC or 3.3Vaux)
- 1.5.1.1 VCC or 3.3Vaux supply requirements
- 1.5.1.2 VCC or 3.3Vaux current consumption in 2G connected-mode
- 1.5.1.3 VCC or 3.3Vaux current consumption in 3G connected mode
- 1.5.1.4 VCC or 3.3Vaux current consumption in LTE connected-mode
- 1.5.1.5 VCC or 3.3Vaux current consumption in cyclic idle/active mode (power saving enabled)
- 1.5.1.6 VCC or 3.3Vaux current consumption in fixed active-mode (power saving disabled)
- 1.5.2 RTC supply input/output (V_BCKP)
- 1.5.3 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC or 3.3Vaux)
- 1.6 System function interfaces
- 1.7 Antenna interface
- 1.8 SIM interface
- 1.9 Data communication interfaces
- 1.10 Audio
- 1.11 General Purpose Input/Output
- 1.12 Mini PCIe specific signals (W_DISABLE#, LED_WWAN#)
- 1.13 Reserved pins (RSVD)
- 1.14 Not connected pins (NC)
- 1.15 System features
- 1.15.1 Network indication
- 1.15.2 Antenna supervisor
- 1.15.3 Jamming detection
- 1.15.4 IP modes of operation
- 1.15.5 Dual stack IPv4/IPv6
- 1.15.6 TCP/IP and UDP/IP
- 1.15.7 FTP
- 1.15.8 HTTP
- 1.15.9 SSL / TLS
- 1.15.10 Bearer Independent Protocol
- 1.15.11 Wi-Fi integration
- 1.15.12 Firmware update Over AT (FOAT)
- 1.15.13 Firmware update Over The Air (FOTA)
- 1.15.14 Smart temperature management
- 1.15.15 SIM Access Profile (SAP)
- 1.15.16 Power saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC or 3.3Vaux)
- 2.2.1.1 General guidelines for VCC or 3.3Vaux supply circuit selection and design
- 2.2.1.2 Guidelines for VCC or 3.3Vaux supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC or 3.3Vaux supply circuit design using a Low Drop-Out linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable Li-Ion or Li-Pol battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery
- 2.2.1.6 Additional guidelines for VCC or 3.3Vaux supply circuit design
- 2.2.1.7 Guidelines for external battery charging circuit
- 2.2.1.8 Guidelines for external battery charging and power path management circuit
- 2.2.1.9 Guidelines for VCC or 3.3Vaux supply layout design
- 2.2.1.10 Guidelines for grounding layout design
- 2.2.2 RTC supply output (V_BCKP)
- 2.2.3 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC or 3.3Vaux)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interface
- 2.6 Data communication interfaces
- 2.7 Audio interface
- 2.8 General Purpose Input/Output
- 2.9 Mini PCIe specific signals (W_DISABLE#, LED_WWAN#)
- 2.10 Reserved pins (RSVD)
- 2.11 Module placement
- 2.12 TOBY-L2 series module footprint and paste mask
- 2.13 MPCI-L2 series module installation
- 2.14 Thermal guidelines
- 2.15 ESD guidelines
- 2.16 Schematic for TOBY-L2 and MPCI-L2 series module integration
- 2.17 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 4.1 Product certification approval overview
- 4.2 US Federal Communications Commission notice
- 4.3 Innovation, Science and Economic Development Canada notice
- 4.4 Brazilian Anatel certification
- 4.5 European Conformance CE mark
- 4.6 Australian Regulatory Compliance Mark
- 4.7 Taiwanese NCC certification
- 4.8 Japanese Giteki certification
- 5 Product testing
- Appendix
- A Migration between TOBY-L1 and TOBY-L2
- B Glossary
- Related documents
- Revision history
- Contact
TOBY-L2 and MPCI-L2 series - System Integration Manual
UBX-13004618 - R26 Design-in
Page 106 of 162
2.6 Data communication interfaces
2.6.1 Universal Serial Bus (USB)
2.6.1.1 Guidelines for USB circuit design
The USB_D+ and USB_D- lines carry the USB serial data and signaling. The lines are used in single ended mode
for full speed signaling handshake, as well as in differential mode for high speed signaling and data transfer.
USB pull-up or pull-down resistors and external series resistors on USB_D+ and USB_D- lines as required by the
USB 2.0 specification [7] are part of the module USB pin driver and do not need to be externally provided.
VUSB_DET functionality is not supported by all the TOBY-L2 series modules product versions: the pin should
be left unconnected or it should not be driven high (for more details, see section 1.9.1.1).
VUSB_DET pin is not available on MPCI-L2 series modules.
Routing the USB pins to a connector, they will be externally accessible on the application device. According to
EMC/ESD requirements of the application, an additional ESD protection device with very low capacitance should
be provided close to accessible point on the line connected to this pin, as described in Figure 54 and Table 40.
The USB interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F).
Higher protection level could be required if the lines are externally accessible and it can be achieved by
mounting a very low capacitance (i.e. less or equal to 1 pF) ESD protection (e.g. Tyco Electronics
PESD0402-140 ESD protection device) on the lines connected to these pins, close to accessible points.
The USB_D+ and USB_D- pins of the modules can be directly connected to the USB host application processor
without additional ESD protections if they are not externally accessible or according to EMC/ESD requirements.
D+
D-
GND
28
USB_D+
27
USB_D-
GND
USB DEVICE
CONNECTOR
VBUS
D+
D-
GND
28
USB_D+
27
USB_D-
GND
USB HOST
PROCESSOR
D+
D-
GND
38
USB_D+
36
USB_D-
GND
USB DEVICE
CONNECTOR
VBUS
TOBY-L2 series TOBY-L2 series
MPCI-L2 series MPCI-L2 series
D+
D-
GND
38
USB_D+
36
USB_D-
GND
USB HOST
PROCESSOR
VBUS
4
VUSB_DET
4
VUSB_DET
D1 D2
D1 D2
VBUS
Figure 54: USB Interface application circuits
Reference
Description
Part Number - Manufacturer
D1, D2
Very Low Capacitance ESD Protection
PESD0402-140 - Tyco Electronics
Table 40: Component for USB application circuits
If the USB interface pins are not used, they can be left unconnected on the application board, but it is
recommended providing accessible test points directly connected to USB_D+ and USB_D- pins.