User's Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.6 System function interfaces
- 1.7 Antenna interface
- 1.8 SIM interface
- 1.9 Serial interfaces
- 1.9.1 Asynchronous serial interface (UART)
- 1.9.1.1 UART features
- 1.9.1.2 UART AT interface configuration
- 1.9.1.3 UART signal behavior
- 1.9.1.4 UART and power-saving
- AT+UPSV=0: power saving disabled, fixed active-mode
- AT+UPSV=1: power saving enabled, cyclic idle/active-mode
- AT+UPSV=2: power saving enabled and controlled by the RTS line
- AT+UPSV=3: power saving enabled and controlled by the DTR line
- Wake up via data reception
- Additional considerations for SARA-U2 modules
- 1.9.1.5 Multiplexer protocol (3GPP 27.010)
- 1.9.2 Auxiliary asynchronous serial interface (UART AUX)
- 1.9.3 USB interface
- 1.9.4 DDC (I2C) interface
- 1.9.1 Asynchronous serial interface (UART)
- 1.10 Audio interface
- 1.11 General Purpose Input/Output (GPIO)
- 1.12 Reserved pins (RSVD)
- 1.13 System features
- 1.13.1 Network indication
- 1.13.2 Antenna detection
- 1.13.3 Jamming detection
- 1.13.4 TCP/IP and UDP/IP
- 1.13.5 FTP
- 1.13.6 HTTP
- 1.13.7 SMTP
- 1.13.8 SSL
- 1.13.9 Dual stack IPv4/IPv6
- 1.13.10 Smart temperature management
- 1.13.11 AssistNow clients and GNSS integration
- 1.13.12 Hybrid positioning and CellLocate®
- 1.13.13 Firmware upgrade Over AT (FOAT)
- 1.13.14 Firmware upgrade Over The Air (FOTA)
- 1.13.15 In-Band modem (eCall / ERA-GLONASS)
- 1.13.16 SIM Access Profile (SAP)
- 1.13.17 Power saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a Low Drop-Out (LDO) linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable Li-Ion or Li-Pol battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for external battery charging circuit
- 2.2.1.8 Guidelines for external battery charging and power path management circuit
- 2.2.1.9 Guidelines for VCC supply layout design
- 2.2.1.10 Guidelines for grounding layout design
- 2.2.2 RTC supply (V_BCKP)
- 2.2.3 Interface supply (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interface
- 2.6 Serial interfaces
- 2.6.1 Asynchronous serial interface (UART)
- 2.6.1.1 Guidelines for UART circuit design
- Providing the full RS-232 functionality (using the complete V.24 link)
- Providing the TXD, RXD, RTS, CTS and DTR lines only (not using the complete V.24 link)
- Providing the TXD, RXD, RTS and CTS lines only (not using the complete V.24 link)
- Providing the TXD and RXD lines only (not using the complete V24 link)
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 Auxiliary asynchronous serial interface (UART AUX)
- 2.6.3 Universal Serial Bus (USB)
- 2.6.4 DDC (I2C) interface
- 2.6.1 Asynchronous serial interface (UART)
- 2.7 Audio interface
- 2.7.1 Analog audio interface
- 2.7.1.1 Guidelines for microphone and speaker connection circuit design (headset / handset modes)
- 2.7.1.2 Guidelines for microphone and loudspeaker connection circuit design (hands-free mode)
- 2.7.1.3 Guidelines for external analog audio device connection circuit design
- 2.7.1.4 Guidelines for analog audio layout design
- 2.7.2 Digital audio interface
- 2.7.1 Analog audio interface
- 2.8 General Purpose Input/Output (GPIO)
- 2.9 Reserved pins (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Thermal guidelines
- 2.13 ESD guidelines
- 2.14 SARA-G350 ATEX and SARA-U270 ATEX integration in explosive atmospheres applications
- 2.15 Schematic for SARA-G3 and SARA-U2 series module integration
- 2.16 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between LISA and SARA-G3 modules
- A.1 Overview
- A.2 Checklist for migration
- A.3 Software migration
- A.4 Hardware migration
- B Migration between SARA-G3 and SARA-U2
- C Glossary
- Related documents
- Revision history
- Contact
SARA-G3 and SARA-U2 series - System Integration Manual
R2R1
GND
U1
SARA-G340 / SARA-G350
SARA
-U2 series
Audio
Codec
SDA
SCL
SDA
SCL
Clock Output
MCLK
GND
R3
C3C2
C1
4
V_INT
VDD
1V8
MICBIAS
C4
R4
C5
C6
EMI1
MICLN
MICLP
Microphone
Connector
EMI2
MIC
C12 C11
J1
MICGND
R5
C8 C7
SPK
Speaker
Connector
OUTP
OUTN
J2
C10 C9
C14
C13
EMI3
EMI4
IRQn
BCLK
LRCLK
SDIN
SDOUT
36
I2S_CLK
34
I2S_WA
35
I2S_TXD
37
I2S_RXD
1V81V8
Application Processor
GND
AT interface
D3
D1
D4
D2
Figure 80: Application circuit for connecting SARA-G3 / SARA-U2 modules with an external audio codec
As in general any external digital audio device compliant to the configuration of the digital audio interface of the
cellular module can be used, various external audio codecs other than the one described in Figure 79, Figure 80
and Table 53 can be used to provide voice capability. For example the Maxim MAX9867 audio codec, the Maxim
MAX9880A audio codec as well as many other parts produced by the same or other various manufacturers
(including Texas Instruments, Wolfson / Cirrus Logic, Freescale, etc) can be used instead of the Maxim MAX9860
audio codec described above, implementing and configuring an appropriate application circuit according to the
specific device and application requirements.
Any external signal connected to the digital audio interface must be tri-stated or set low when the module
is in power-down mode and during the module power-on sequence (at least until the activation of the
V_INT supply output of the module), to avoid latch-up of circuits and allow a proper boot of the module.
If the external signals connected to the cellular module cannot be tri-stated or set low, insert a multi
channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the
two-circuit connections and set to high impedance during module power down mode and during the
module power-on sequence.
ESD sensitivity rating of I
2
S interface pins is 1 kV (Human Body Model according to JESD22-A114). Higher
protection level could be required if the lines are externally accessible on the application board. Higher
protection level can be achieved by mounting a general purpose ESD protection (e.g. EPCOS
CA05P4S14THSG varistor array) close to accessible points.
If the I
2
S digital audio pins are not used, they can be left unconnected on the application board.
2.7.2.2 Guidelines for digital audio layout design
The I
2
S interfaces lines (I2S_CLK, I2S_RX, I2S_TX, I2S_WA) require the same consideration regarding
electro-magnetic interference as any other digital interface. Keep the traces short and avoid coupling with RF
lines / parts or sensitive analog inputs, since the signals can cause the radiation of some harmonics of the digital
data frequency.
UBX-13000995 - R12 Early Production Information Design-in
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