User's Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.6 System function interfaces
- 1.7 Antenna interface
- 1.8 SIM interface
- 1.9 Serial interfaces
- 1.9.1 Asynchronous serial interface (UART)
- 1.9.1.1 UART features
- 1.9.1.2 UART AT interface configuration
- 1.9.1.3 UART signal behavior
- 1.9.1.4 UART and power-saving
- AT+UPSV=0: power saving disabled, fixed active-mode
- AT+UPSV=1: power saving enabled, cyclic idle/active-mode
- AT+UPSV=2: power saving enabled and controlled by the RTS line
- AT+UPSV=3: power saving enabled and controlled by the DTR line
- Wake up via data reception
- Additional considerations for SARA-U2 modules
- 1.9.1.5 Multiplexer protocol (3GPP 27.010)
- 1.9.2 Auxiliary asynchronous serial interface (UART AUX)
- 1.9.3 USB interface
- 1.9.4 DDC (I2C) interface
- 1.9.1 Asynchronous serial interface (UART)
- 1.10 Audio interface
- 1.11 General Purpose Input/Output (GPIO)
- 1.12 Reserved pins (RSVD)
- 1.13 System features
- 1.13.1 Network indication
- 1.13.2 Antenna detection
- 1.13.3 Jamming detection
- 1.13.4 TCP/IP and UDP/IP
- 1.13.5 FTP
- 1.13.6 HTTP
- 1.13.7 SMTP
- 1.13.8 SSL
- 1.13.9 Dual stack IPv4/IPv6
- 1.13.10 Smart temperature management
- 1.13.11 AssistNow clients and GNSS integration
- 1.13.12 Hybrid positioning and CellLocateTM
- 1.13.13 Firmware upgrade Over AT (FOAT)
- 1.13.14 Firmware upgrade Over The Air (FOTA)
- 1.13.15 In-Band modem (eCall / ERA-GLONASS)
- 1.13.16 SIM Access Profile (SAP)
- 1.13.17 Power saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a Low Drop-Out (LDO) linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable Li-Ion or Li-Pol battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for external battery charging circuit
- 2.2.1.8 Guidelines for external battery charging and power path management circuit
- 2.2.1.9 Guidelines for VCC supply layout design
- 2.2.1.10 Guidelines for grounding layout design
- 2.2.2 RTC supply (V_BCKP)
- 2.2.3 Interface supply (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interface
- 2.6 Serial interfaces
- 2.6.1 Asynchronous serial interface (UART)
- 2.6.1.1 Guidelines for UART circuit design
- Providing the full RS-232 functionality (using the complete V.24 link)
- Providing the TXD, RXD, RTS, CTS and DTR lines only (not using the complete V.24 link)
- Providing the TXD, RXD, RTS and CTS lines only (not using the complete V.24 link)
- Providing the TXD and RXD lines only (not using the complete V24 link)
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 Auxiliary asynchronous serial interface (UART AUX)
- 2.6.3 Universal Serial Bus (USB)
- 2.6.4 DDC (I2C) interface
- 2.6.1 Asynchronous serial interface (UART)
- 2.7 Audio interface
- 2.7.1 Analog audio interface
- 2.7.1.1 Guidelines for microphone and speaker connection circuit design (headset / handset modes)
- 2.7.1.2 Guidelines for microphone and loudspeaker connection circuit design (hands-free mode)
- 2.7.1.3 Guidelines for external analog audio device connection circuit design
- 2.7.1.4 Guidelines for analog audio layout design
- 2.7.2 Digital audio interface
- 2.7.1 Analog audio interface
- 2.8 General Purpose Input/Output (GPIO)
- 2.9 Reserved pins (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Thermal guidelines
- 2.13 ESD guidelines
- 2.14 SARA-G350 ATEX integration in explosive atmospheres applications
- 2.15 Schematic for SARA-G3 and SARA-U2 series module integration
- 2.16 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between LISA and SARA-G3 modules
- A.1 Overview
- A.2 Checklist for migration
- A.3 Software migration
- A.4 Hardware migration
- B Migration between SARA-G3 and SARA-U2
- C Glossary
- Related documents
- Revision history
- Contact
SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R08 Objective Specification Design-in
Page 96 of 188
2.3 System functions interfaces
2.3.1 Module power-on (PWR_ON)
2.3.1.1 Guidelines for PWR_ON circuit design
Connecting the PWR_ON input to a push button that shorts the PWR_ON pin to ground, provide an external
pull-up resistor (e.g. 100 kΩ) biased by the V_BCKP supply pin of the module, as described in Figure 44 and
Table 23. Connecting the PWR_ON input to a push button, the pin will be externally accessible on the
application device: according to EMC/ESD requirements of the application, provide an additional ESD protection
(e.g. EPCOS CA05P4S14THSG varistor array) on the line connected to this pin, close to accessible point.
The PWR_ON pin has high input impedance and is weakly pulled to the high level on the module. Avoid
keeping it floating in a noisy environment. To hold the high logic level stable, the PWR_ON pin must be
connected to a pull-up resistor (e.g. 100 kΩ) biased by the V_BCKP supply pin of the module.
ESD sensitivity rating of the PWR_ON pin is 1 kV (Human Body Model according to JESD22-A114). Higher
protection level can be required if the line is externally accessible on the application board, e.g. if an
accessible push button is directly connected to PWR_ON pin. Higher protection level can be achieved by
mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to accessible point.
When connecting the PWR_ON input to an external device (e.g. application processor), use an open drain
output on the external device with an external pull-up resistor (e.g. 100 kΩ) biased by the V_BCKP supply pin of
the module, as described in Figure 44 and Table 23.
A compatible push-pull output of an application processor can also be used: in this case the pull-up can be
provided to pull the PWR_ON level high when the application processor is switched off. If the high-level voltage
of the push-pull output pin of the application processor is greater than the maximum input voltage operating
range of the V_BCKP pin (refer to the SARA-G3 series Data Sheet [1] and the SARA-U2 series Data Sheet [2]),
the V_BCKP supply cannot be used to bias the pull-up resistor: the supply rail of the application processor or the
module VCC supply could be used, but this increases the V_BCKP (RTC supply) current consumption when the
module is in not-powered mode (VCC supply not present). Using a push-pull output of the external device, take
care to fix the proper level in all the possible scenarios to avoid an inappropriate module switch-on.
SARA-G3 series
SARA-U2 series
Rext
2
V_BCKP
15
PWR_ON
Power-on
push button
ESD
Open
Drain
Output
Application
Processor
SARA-G3 series
SARA-U2 series
Rext
2
V_BCKP
15
PWR_ON
TP
TP
Figure 44: PWR_ON application circuits using a push button and an open drain output of an application processor
Reference
Description
Remarks
Rext
100 kΩ Resistor 0402 5% 0.1 W
External pull-up resistor
ESD
CT0402S14AHSG - EPCOS
Varistor array for ESD protection
Table 23: Example of pull-up resistor and ESD protection for the PWR_ON application circuit
It is recommended to provide direct access to the PWR_ON pin on the application board by means of
accessible testpoint directly connected to the PWR_ON pin.