User's Manual

SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R08 Objective Specification Design-in
Page 87 of 188
2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery
The characteristics of a primary (non-rechargeable) battery connected to VCC pins should meet the following
prerequisites to comply with the module VCC requirements summarized in Table 7:
 Maximum pulse and DC discharge current: the non-rechargeable battery with its output circuit must be
capable of delivering to VCC pins the specified maximum peak / pulse current with 1/8 duty cycle, and a DC
current greater than the module maximum average current consumption (refer to the SARA-G3 series Data
Sheet [1] or the SARA-U2 series Data Sheet [2]). The maximum pulse and the maximum DC discharge
current is not always reported in battery data sheets, but the maximum DC discharge current is typically
almost equal to the battery capacity in Amp-hours divided by 1 hour
 DC series resistance: the non-rechargeable battery with its output circuit must be capable of avoiding a
VCC voltage drop greater than 400 mV during transmit bursts
2.2.1.6 Additional guidelines for VCC supply circuit design
To reduce voltage drops, use a low impedance power source. The resistance of the power supply lines
(connected to the VCC and GND pins of the module) on the application board and battery pack should also be
considered and minimized: cabling and routing must be as short as possible to minimize power losses.
Three pins are allocated for VCC supply. Another twenty pins are designated for GND connection. Even if all the
VCC pins and all the GND pins are internally connected within the module, it is recommended to properly
connect all of them to supply the module to minimize series resistance losses.
To avoid voltage drop undershoot and overshoot at the start and end of a transmit burst during a single-slot 2G
voice/data call (when current consumption on the VCC supply can rise up to the maximum peak / pulse current
specified in the SARA-G3 series Data Sheet [1] or in the SARA-U2 series Data Sheet [2]), place a bypass capacitor
with large capacitance (more than 100 µF) and low ESR near the VCC pins, for example:
 330 µF capacitance, 45 m ESR (e.g. KEMET T520D337M006ATE045, Tantalum Capacitor)
The use of very large capacitors (i.e. greater then 1000 µF) on the VCC line should be carefully evaluated, since
the voltage at the VCC pins voltage must ramp from 2.5 V to 3.2 V in less than 1 ms to switch on the SARA-U2
modules or in less than 4 ms to switch on the SARA-G3 modules by applying VCC supply, that otherwise can be
switched on by forcing a low level on the RESET_N pin during the VCC rising edge and then releasing the
RESET_N pin when the VCC supply voltage stabilizes at its proper nominal value.
To reduce voltage ripple and noise, especially if the application device integrates an internal antenna, place the
following bypass capacitors near the VCC pins:
 100 nF capacitor (e.g Murata GRM155R61C104K) to filter digital logic noise from clocks and data sources
 10 nF capacitor (e.g. Murata GRM155R71C103K) to filter digital logic noise from clocks and data sources
 56 pF capacitor with Self-Resonant Frequency in 800/900 MHz range (e.g. Murata GRM1555C1E560J) to
filter transmission EMI in the GSM/EGSM bands
 15 pF capacitor with Self-Resonant Frequency in 1800/1900 MHz range (e.g. Murata GRM1555C1E150J) to
filter transmission EMI in the DCS/PCS bands
A series ferrite bead for GHz band noise (e.g. Murata BLM18EG221SN1) can be placed close to the VCC pins of
the module for additional noise filtering, but in general it is not strictly required.
Figure 39 shows the complete configuration but the mounting of each single component depends on the
application design: it is recommended to provide all the VCC bypass capacitors as described in Figure 39
and Table 19 if the application device integrates an internal antenna.