User's Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.6 System function interfaces
- 1.7 Antenna interface
- 1.8 SIM interface
- 1.9 Serial interfaces
- 1.9.1 Asynchronous serial interface (UART)
- 1.9.1.1 UART features
- 1.9.1.2 UART AT interface configuration
- 1.9.1.3 UART signal behavior
- 1.9.1.4 UART and power-saving
- AT+UPSV=0: power saving disabled, fixed active-mode
- AT+UPSV=1: power saving enabled, cyclic idle/active-mode
- AT+UPSV=2: power saving enabled and controlled by the RTS line
- AT+UPSV=3: power saving enabled and controlled by the DTR line
- Wake up via data reception
- Additional considerations for SARA-U2 modules
- 1.9.1.5 Multiplexer protocol (3GPP 27.010)
- 1.9.2 Auxiliary asynchronous serial interface (UART AUX)
- 1.9.3 USB interface
- 1.9.4 DDC (I2C) interface
- 1.9.1 Asynchronous serial interface (UART)
- 1.10 Audio interface
- 1.11 General Purpose Input/Output (GPIO)
- 1.12 Reserved pins (RSVD)
- 1.13 System features
- 1.13.1 Network indication
- 1.13.2 Antenna detection
- 1.13.3 Jamming detection
- 1.13.4 TCP/IP and UDP/IP
- 1.13.5 FTP
- 1.13.6 HTTP
- 1.13.7 SMTP
- 1.13.8 SSL
- 1.13.9 Dual stack IPv4/IPv6
- 1.13.10 Smart temperature management
- 1.13.11 AssistNow clients and GNSS integration
- 1.13.12 Hybrid positioning and CellLocateTM
- 1.13.13 Firmware upgrade Over AT (FOAT)
- 1.13.14 Firmware upgrade Over The Air (FOTA)
- 1.13.15 In-Band modem (eCall / ERA-GLONASS)
- 1.13.16 SIM Access Profile (SAP)
- 1.13.17 Power saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a Low Drop-Out (LDO) linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable Li-Ion or Li-Pol battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for external battery charging circuit
- 2.2.1.8 Guidelines for external battery charging and power path management circuit
- 2.2.1.9 Guidelines for VCC supply layout design
- 2.2.1.10 Guidelines for grounding layout design
- 2.2.2 RTC supply (V_BCKP)
- 2.2.3 Interface supply (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interface
- 2.6 Serial interfaces
- 2.6.1 Asynchronous serial interface (UART)
- 2.6.1.1 Guidelines for UART circuit design
- Providing the full RS-232 functionality (using the complete V.24 link)
- Providing the TXD, RXD, RTS, CTS and DTR lines only (not using the complete V.24 link)
- Providing the TXD, RXD, RTS and CTS lines only (not using the complete V.24 link)
- Providing the TXD and RXD lines only (not using the complete V24 link)
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 Auxiliary asynchronous serial interface (UART AUX)
- 2.6.3 Universal Serial Bus (USB)
- 2.6.4 DDC (I2C) interface
- 2.6.1 Asynchronous serial interface (UART)
- 2.7 Audio interface
- 2.7.1 Analog audio interface
- 2.7.1.1 Guidelines for microphone and speaker connection circuit design (headset / handset modes)
- 2.7.1.2 Guidelines for microphone and loudspeaker connection circuit design (hands-free mode)
- 2.7.1.3 Guidelines for external analog audio device connection circuit design
- 2.7.1.4 Guidelines for analog audio layout design
- 2.7.2 Digital audio interface
- 2.7.1 Analog audio interface
- 2.8 General Purpose Input/Output (GPIO)
- 2.9 Reserved pins (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Thermal guidelines
- 2.13 ESD guidelines
- 2.14 SARA-G350 ATEX integration in explosive atmospheres applications
- 2.15 Schematic for SARA-G3 and SARA-U2 series module integration
- 2.16 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between LISA and SARA-G3 modules
- A.1 Overview
- A.2 Checklist for migration
- A.3 Software migration
- A.4 Hardware migration
- B Migration between SARA-G3 and SARA-U2
- C Glossary
- Related documents
- Revision history
- Contact
SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R08 Objective Specification System description
Page 61 of 188
1.10.3 Voice-band processing system
1.10.3.1 SARA-G340 / SARA-G350 modules audio processing
The voice-band processing on the SARA-G340 / SARA-G350 modules is implemented in the DSP core inside the
baseband chipset. The analog audio front-end of the chipset is connected to the digital system through 16 bit
ADC converters in the uplink path, and through 16 bit DAC converters in the downlink path. External digital
audio devices can directly be interfaced to the DSP digital processing part via the I
2
S digital interface. The analog
amplifiers are skipped in this case.
The voice-band processing system can be split up into three different blocks:
Sample-based Voice-band Processing (single sample processed at 8 kHz, every 125 µs)
Frame-based Voice-band Processing (frames of 160 samples are processed every 20 ms)
MIDI synthesizer running at 47.6 kHz
These three blocks are connected by buffers and sample rate converters (for 8 to 47.6 kHz conversion)
I2S_RXD
Switch
MIC
Uplink
Analog Gain
Uplink
Filter 2
Uplink
Filter 1
To
Radio TX
Uplink
Digital Gain
Downlink
Filter 1
Downlink
Filter 2
MIDI
Player
SPK
Switch
I2Sx TX
I2S_TXD
Scal_Rec
Digital Gain
SPK
Analog Gain
Gain_Out
Digital Gain
From
Radio RX
Speech
Level
I2Sx RX
Sample Based Processing Frame Based Processing
Circular
Buffer
Sidetone
Digital Gain
DAC
ADC
Tone
Generator
AMR
Player
Hands-Free
Voiceband Sample Buffer
Figure 28: SARA-G340 / SARA-G350 modules audio processing system block diagram
The sample-based voice-band processing main task is to transfer the voice-band samples from either analog
audio front-end uplink path or I2Sx RX path to the Voice-band Sample Buffer and from the Voice-band Sample
Buffer to the analog audio front-end downlink path and/or I2Sx TX path. While doing this the samples are scaled
by digital gains and processed by digital filters both in the uplink and downlink direction and the sidetone is
generated mixing scaled uplink samples to the downlink samples (refer to the u-blox AT Commands Manual [3],
+UUBF, +UDBF, +UMGC, +USGC, +USTN commands).
The frame-based voice-band processing implements the Hands-Free algorithm. This consists of the Echo
Canceller, the Automatic Gain Control and the Noise Suppressor. Hands-Free algorithm acts on the uplink signal
only. Algorithms are configurable with AT commands (refer to the u-blox AT Commands Manual [3], +UHFP
command). The frame-based voice-band processing also implements an AMR player. The speech uplink path
final block before radio transmission is the speech encoder. Symmetrically, on downlink path, the starting block
is the speech decoder which extracts speech signal from the radio receiver.
The circular buffer is a 3000 word buffer to store and mix the voice-band samples from Midi synthesizer. The
buffer has a circular structure, so that when the write pointer reaches the end of the buffer, it is wrapped to the
begin address of the buffer.