User's Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.6 System function interfaces
- 1.7 Antenna interface
- 1.8 SIM interface
- 1.9 Serial interfaces
- 1.9.1 Asynchronous serial interface (UART)
- 1.9.1.1 UART features
- 1.9.1.2 UART AT interface configuration
- 1.9.1.3 UART signal behavior
- 1.9.1.4 UART and power-saving
- AT+UPSV=0: power saving disabled, fixed active-mode
- AT+UPSV=1: power saving enabled, cyclic idle/active-mode
- AT+UPSV=2: power saving enabled and controlled by the RTS line
- AT+UPSV=3: power saving enabled and controlled by the DTR line
- Wake up via data reception
- Additional considerations for SARA-U2 modules
- 1.9.1.5 Multiplexer protocol (3GPP 27.010)
- 1.9.2 Auxiliary asynchronous serial interface (UART AUX)
- 1.9.3 USB interface
- 1.9.4 DDC (I2C) interface
- 1.9.1 Asynchronous serial interface (UART)
- 1.10 Audio interface
- 1.11 General Purpose Input/Output (GPIO)
- 1.12 Reserved pins (RSVD)
- 1.13 System features
- 1.13.1 Network indication
- 1.13.2 Antenna detection
- 1.13.3 Jamming detection
- 1.13.4 TCP/IP and UDP/IP
- 1.13.5 FTP
- 1.13.6 HTTP
- 1.13.7 SMTP
- 1.13.8 SSL
- 1.13.9 Dual stack IPv4/IPv6
- 1.13.10 Smart temperature management
- 1.13.11 AssistNow clients and GNSS integration
- 1.13.12 Hybrid positioning and CellLocateTM
- 1.13.13 Firmware upgrade Over AT (FOAT)
- 1.13.14 Firmware upgrade Over The Air (FOTA)
- 1.13.15 In-Band modem (eCall / ERA-GLONASS)
- 1.13.16 SIM Access Profile (SAP)
- 1.13.17 Power saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a Low Drop-Out (LDO) linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable Li-Ion or Li-Pol battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for external battery charging circuit
- 2.2.1.8 Guidelines for external battery charging and power path management circuit
- 2.2.1.9 Guidelines for VCC supply layout design
- 2.2.1.10 Guidelines for grounding layout design
- 2.2.2 RTC supply (V_BCKP)
- 2.2.3 Interface supply (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interface
- 2.6 Serial interfaces
- 2.6.1 Asynchronous serial interface (UART)
- 2.6.1.1 Guidelines for UART circuit design
- Providing the full RS-232 functionality (using the complete V.24 link)
- Providing the TXD, RXD, RTS, CTS and DTR lines only (not using the complete V.24 link)
- Providing the TXD, RXD, RTS and CTS lines only (not using the complete V.24 link)
- Providing the TXD and RXD lines only (not using the complete V24 link)
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 Auxiliary asynchronous serial interface (UART AUX)
- 2.6.3 Universal Serial Bus (USB)
- 2.6.4 DDC (I2C) interface
- 2.6.1 Asynchronous serial interface (UART)
- 2.7 Audio interface
- 2.7.1 Analog audio interface
- 2.7.1.1 Guidelines for microphone and speaker connection circuit design (headset / handset modes)
- 2.7.1.2 Guidelines for microphone and loudspeaker connection circuit design (hands-free mode)
- 2.7.1.3 Guidelines for external analog audio device connection circuit design
- 2.7.1.4 Guidelines for analog audio layout design
- 2.7.2 Digital audio interface
- 2.7.1 Analog audio interface
- 2.8 General Purpose Input/Output (GPIO)
- 2.9 Reserved pins (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Thermal guidelines
- 2.13 ESD guidelines
- 2.14 SARA-G350 ATEX integration in explosive atmospheres applications
- 2.15 Schematic for SARA-G3 and SARA-U2 series module integration
- 2.16 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between LISA and SARA-G3 modules
- A.1 Overview
- A.2 Checklist for migration
- A.3 Software migration
- A.4 Hardware migration
- B Migration between SARA-G3 and SARA-U2
- C Glossary
- Related documents
- Revision history
- Contact
SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R08 Objective Specification System description
Page 48 of 188
AT+UPSV
HW flow control
RTS line
DTR line
Communication during idle-mode and wake up
3
Enabled (AT&K3)
ON
ON
Data sent by the DTE is correctly received by the module.
Data sent by the module is correctly received by the DTE.
3
Enabled (AT&K3)
ON
OFF
Data sent by the DTE is lost by the module.
Data sent by the module is correctly received by the DTE.
3
Enabled (AT&K3)
OFF
ON
Data sent by the DTE is correctly received by the module.
Data sent by the module is buffered by the module and will be correctly
received by the DTE when it is ready to receive data (i.e. RTS line will be ON).
3
Enabled (AT&K3)
OFF
OFF
Data sent by the DTE is lost by the module.
Data sent by the module is buffered by the module and will be correctly
received by the DTE when it is ready to receive data (i.e. RTS line will be ON).
3
Disabled (AT&K0)
ON or OFF
ON
Data sent by the DTE is correctly received by the module.
Data sent by the module is correctly received by the DTE if it is ready to receive
data, otherwise data are lost.
3
Disabled (AT&K0)
ON or OFF
OFF
Data sent by the DTE is lost by the module.
Data sent by the module is correctly received by the DTE if it is ready to receive
data, otherwise data are lost.
Table 12: UART and power-saving summary
AT+UPSV=0: power saving disabled, fixed active-mode
The module does not enter idle-mode and the UART interface is enabled (data can be sent and received): the
CTS line is always held in the ON state after UART initialization. This is the default configuration.
AT+UPSV=1: power saving enabled, cyclic idle/active-mode
On SARA-G3 modules, when the AT+UPSV=1 command is issued by the DTE, the UART is disabled after the
timeout set by the second parameter of the +UPSV AT command (for more details see u-blox AT commands
Manual [3]).
On SARA-U2 modules, when the AT+UPSV=1 command is issued by the DTE, the UART is immediately disabled.
Afterwards, the UART of SARA-G3 and SARA-U2 series modules is periodically enabled to receive or send data
and, if data has not been received or sent over the UART, the interface is automatically disabled whenever
possible according to the timeout configured by the second parameter of the +UPSV AT command.
The module automatically enters the low power idle-mode whenever possible but it wakes up to active-mode
according to the UART periodic wake up so that the module cyclically enters the low power idle-mode and the
active-mode. Additionally, the module wakes up to active-mode according to any required activity related to the
network or any other required activity related to the functions / interfaces of the module.
The UART is enabled, and the module does not enter low power idle-mode, in the following cases:
During the periodic UART wake up to receive or send data
If the module needs to transmit some data over the UART (e.g. URC)
During a CSD data call and a PSD data call with external context activation
On SARA-G3 modules, during a voice call
If a character is sent by the DTE with HW flow control disabled, the first character sent causes the system
wake-up due to the “wake up via data reception” feature described in the following subsection, and the
UART will be then kept enabled after the last data received according to the timeout set by the second
parameter of the AT+UPSV=1 command
The module, outside an active call, periodically wakes up from idle-mode to active-mode to monitor the paging
channel of the current base station (paging block reception), according to 2G or 3G discontinuous reception
(DRX) specification.