User's Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.6 System function interfaces
- 1.7 Antenna interface
- 1.8 SIM interface
- 1.9 Serial interfaces
- 1.9.1 Asynchronous serial interface (UART)
- 1.9.1.1 UART features
- 1.9.1.2 UART AT interface configuration
- 1.9.1.3 UART signal behavior
- 1.9.1.4 UART and power-saving
- AT+UPSV=0: power saving disabled, fixed active-mode
- AT+UPSV=1: power saving enabled, cyclic idle/active-mode
- AT+UPSV=2: power saving enabled and controlled by the RTS line
- AT+UPSV=3: power saving enabled and controlled by the DTR line
- Wake up via data reception
- Additional considerations for SARA-U2 modules
- 1.9.1.5 Multiplexer protocol (3GPP 27.010)
- 1.9.2 Auxiliary asynchronous serial interface (UART AUX)
- 1.9.3 USB interface
- 1.9.4 DDC (I2C) interface
- 1.9.1 Asynchronous serial interface (UART)
- 1.10 Audio interface
- 1.11 General Purpose Input/Output (GPIO)
- 1.12 Reserved pins (RSVD)
- 1.13 System features
- 1.13.1 Network indication
- 1.13.2 Antenna detection
- 1.13.3 Jamming detection
- 1.13.4 TCP/IP and UDP/IP
- 1.13.5 FTP
- 1.13.6 HTTP
- 1.13.7 SMTP
- 1.13.8 SSL
- 1.13.9 Dual stack IPv4/IPv6
- 1.13.10 Smart temperature management
- 1.13.11 AssistNow clients and GNSS integration
- 1.13.12 Hybrid positioning and CellLocateTM
- 1.13.13 Firmware upgrade Over AT (FOAT)
- 1.13.14 Firmware upgrade Over The Air (FOTA)
- 1.13.15 In-Band modem (eCall / ERA-GLONASS)
- 1.13.16 SIM Access Profile (SAP)
- 1.13.17 Power saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a Low Drop-Out (LDO) linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable Li-Ion or Li-Pol battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for external battery charging circuit
- 2.2.1.8 Guidelines for external battery charging and power path management circuit
- 2.2.1.9 Guidelines for VCC supply layout design
- 2.2.1.10 Guidelines for grounding layout design
- 2.2.2 RTC supply (V_BCKP)
- 2.2.3 Interface supply (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interface
- 2.6 Serial interfaces
- 2.6.1 Asynchronous serial interface (UART)
- 2.6.1.1 Guidelines for UART circuit design
- Providing the full RS-232 functionality (using the complete V.24 link)
- Providing the TXD, RXD, RTS, CTS and DTR lines only (not using the complete V.24 link)
- Providing the TXD, RXD, RTS and CTS lines only (not using the complete V.24 link)
- Providing the TXD and RXD lines only (not using the complete V24 link)
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 Auxiliary asynchronous serial interface (UART AUX)
- 2.6.3 Universal Serial Bus (USB)
- 2.6.4 DDC (I2C) interface
- 2.6.1 Asynchronous serial interface (UART)
- 2.7 Audio interface
- 2.7.1 Analog audio interface
- 2.7.1.1 Guidelines for microphone and speaker connection circuit design (headset / handset modes)
- 2.7.1.2 Guidelines for microphone and loudspeaker connection circuit design (hands-free mode)
- 2.7.1.3 Guidelines for external analog audio device connection circuit design
- 2.7.1.4 Guidelines for analog audio layout design
- 2.7.2 Digital audio interface
- 2.7.1 Analog audio interface
- 2.8 General Purpose Input/Output (GPIO)
- 2.9 Reserved pins (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Thermal guidelines
- 2.13 ESD guidelines
- 2.14 SARA-G350 ATEX integration in explosive atmospheres applications
- 2.15 Schematic for SARA-G3 and SARA-U2 series module integration
- 2.16 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between LISA and SARA-G3 modules
- A.1 Overview
- A.2 Checklist for migration
- A.3 Software migration
- A.4 Hardware migration
- B Migration between SARA-G3 and SARA-U2
- C Glossary
- Related documents
- Revision history
- Contact
SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R08 Objective Specification System description
Page 44 of 188
RTS signal behavior
The hardware flow control input (RTS line) is set by default to the OFF state (high level) at UART initialization.
The module then holds the RTS line in the OFF state if the line is not activated by the DTE: an active pull-up is
enabled inside the module on the RTS input.
If the HW flow control is enabled, as it is by default, the module monitors the RTS line to detect permission from
the DTE to send data to the DTE itself. If the RTS line is set to the OFF state, any on-going data transmission
from the module is interrupted until the subsequent RTS line change to the ON state.
The DTE must still be able to accept a certain number of characters after the RTS line is set to the OFF
state: the module guarantees the transmission interruption within two characters from RTS state change.
Module behavior according to RTS hardware flow control status can be configured by AT commands (for more
details, see u-blox AT Commands Manual [3], AT&K, AT\Q, AT+IFC command descriptions).
If AT+UPSV=2 is set and HW flow control is disabled, the module monitors the RTS line to manage the power
saving configuration:
When an OFF-to-ON transition occurs on the RTS input line, the UART is enabled and the module wakes up
to active-mode: after ~20 ms from the OFF-to-ON transition the UART / module wake up is completed and
data can be received without loss. The module cannot enter the low power idle-mode and the UART is kept
enabled as long as the RTS input line is held in the ON state
If the RTS input line is set to the OFF state by the DTE, the UART is disabled (held in low power mode) and
the module automatically enters low power idle-mode whenever possible
For more details, see section 1.9.1.4 and u-blox AT Commands Manual [3], AT+UPSV command.
DSR signal behavior
If AT&S1 is set, as it is by default, the DSR module output line is set by default to the OFF state (high level) at
UART initialization. The DSR line is then set to the OFF state when the module is in command mode or in online
command mode and is set to the ON state when the module is in data mode (see the u-blox AT Commands
Manual [3] for the definition of the interface data mode, command mode and online command mode).
If AT&S0 is set, the DSR module output line is set by default to the ON state (low level) at UART initialization and
is then always held in the ON state.
DTR signal behavior
The DTR module input line is set by default to the OFF state (high level) at UART initialization. The module then
holds the DTR line in the OFF state if the line is not activated by the DTE: an active pull-up is enabled inside the
module on the DTR input.
Module behavior according to DTR status can be changed by AT command (for more details, see u-blox AT
Commands Manual [3], AT&D command description).
If AT+UPSV=3 is set, the DTR line is monitored by the module to manage the power saving configuration:
When an OFF-to-ON transition occurs on the DTR input line, the UART is enabled and the module wakes up
to active-mode: after ~20 ms from the OFF-to-ON transition the UART / module wake up is completed and
data can be received without loss. The module cannot enter the low power idle-mode and the UART is kept
enabled as long as the DTR input line is held in the ON state
If the DTR input line is set to the OFF state by the DTE, the UART is disabled (held in low power mode) and
the module automatically enters low power idle-mode whenever possible
For more details, see section 1.9.1.4 and u-blox AT Commands Manual [3], AT+UPSV command.
AT+UPSV=3 power saving configuration control by the DTR input is not supported by SARA-G3 modules.