User's Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.6 System function interfaces
- 1.7 Antenna interface
- 1.8 SIM interface
- 1.9 Serial interfaces
- 1.9.1 Asynchronous serial interface (UART)
- 1.9.1.1 UART features
- 1.9.1.2 UART AT interface configuration
- 1.9.1.3 UART signal behavior
- 1.9.1.4 UART and power-saving
- AT+UPSV=0: power saving disabled, fixed active-mode
- AT+UPSV=1: power saving enabled, cyclic idle/active-mode
- AT+UPSV=2: power saving enabled and controlled by the RTS line
- AT+UPSV=3: power saving enabled and controlled by the DTR line
- Wake up via data reception
- Additional considerations for SARA-U2 modules
- 1.9.1.5 Multiplexer protocol (3GPP 27.010)
- 1.9.2 Auxiliary asynchronous serial interface (UART AUX)
- 1.9.3 USB interface
- 1.9.4 DDC (I2C) interface
- 1.9.1 Asynchronous serial interface (UART)
- 1.10 Audio interface
- 1.11 General Purpose Input/Output (GPIO)
- 1.12 Reserved pins (RSVD)
- 1.13 System features
- 1.13.1 Network indication
- 1.13.2 Antenna detection
- 1.13.3 Jamming detection
- 1.13.4 TCP/IP and UDP/IP
- 1.13.5 FTP
- 1.13.6 HTTP
- 1.13.7 SMTP
- 1.13.8 SSL
- 1.13.9 Dual stack IPv4/IPv6
- 1.13.10 Smart temperature management
- 1.13.11 AssistNow clients and GNSS integration
- 1.13.12 Hybrid positioning and CellLocateTM
- 1.13.13 Firmware upgrade Over AT (FOAT)
- 1.13.14 Firmware upgrade Over The Air (FOTA)
- 1.13.15 In-Band modem (eCall / ERA-GLONASS)
- 1.13.16 SIM Access Profile (SAP)
- 1.13.17 Power saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a Low Drop-Out (LDO) linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable Li-Ion or Li-Pol battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for external battery charging circuit
- 2.2.1.8 Guidelines for external battery charging and power path management circuit
- 2.2.1.9 Guidelines for VCC supply layout design
- 2.2.1.10 Guidelines for grounding layout design
- 2.2.2 RTC supply (V_BCKP)
- 2.2.3 Interface supply (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interface
- 2.6 Serial interfaces
- 2.6.1 Asynchronous serial interface (UART)
- 2.6.1.1 Guidelines for UART circuit design
- Providing the full RS-232 functionality (using the complete V.24 link)
- Providing the TXD, RXD, RTS, CTS and DTR lines only (not using the complete V.24 link)
- Providing the TXD, RXD, RTS and CTS lines only (not using the complete V.24 link)
- Providing the TXD and RXD lines only (not using the complete V24 link)
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 Auxiliary asynchronous serial interface (UART AUX)
- 2.6.3 Universal Serial Bus (USB)
- 2.6.4 DDC (I2C) interface
- 2.6.1 Asynchronous serial interface (UART)
- 2.7 Audio interface
- 2.7.1 Analog audio interface
- 2.7.1.1 Guidelines for microphone and speaker connection circuit design (headset / handset modes)
- 2.7.1.2 Guidelines for microphone and loudspeaker connection circuit design (hands-free mode)
- 2.7.1.3 Guidelines for external analog audio device connection circuit design
- 2.7.1.4 Guidelines for analog audio layout design
- 2.7.2 Digital audio interface
- 2.7.1 Analog audio interface
- 2.8 General Purpose Input/Output (GPIO)
- 2.9 Reserved pins (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Thermal guidelines
- 2.13 ESD guidelines
- 2.14 SARA-G350 ATEX integration in explosive atmospheres applications
- 2.15 Schematic for SARA-G3 and SARA-U2 series module integration
- 2.16 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between LISA and SARA-G3 modules
- A.1 Overview
- A.2 Checklist for migration
- A.3 Software migration
- A.4 Hardware migration
- B Migration between SARA-G3 and SARA-U2
- C Glossary
- Related documents
- Revision history
- Contact
SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R08 Objective Specification Appendix
Page 182 of 188
SARA-G3
SARA-U2
Pin No
Pin Name
Description
Pin Name
Description
Remarks for migration
25
GPIO4 / RSVD
1.8 V GPIO / Reserved
Default: GNSS RTC sharing
Driver strength: 6 mA
Internal pull-down: ~35 k
GPIO4
1.8 V GPIO
Default: GNSS RTC sharing
Driver strength: 6 mA
Internal pull-down: ~9 k
No functional difference
26
SDA / RSVD
I
2
C Data I/O / Reserved
1.8 V, open drain
Driver strength: 3 mA
SDA
I
2
C Data I/O
1.8 V, open drain
Driver strength: 1 mA
No functional difference
27
SCL / RSVD
I
2
C Clock Output / Reserved
1.8 V, open drain
Driver strength: 3 mA
SCL
I
2
C Clock Output
1.8 V, open drain
Driver strength: 1 mA
No functional difference
28
RXD_AUX
Aux UART Data Out
1.8 V, Driver strength: 5 mA
USB_D-
USB Data I/O (D-)
High-Speed USB 2.0
USB instead of Auxiliary UART
29
TXD_AUX
Aux UART Data In
1.8 V, Internal pull-up:~18 k
USB_D+
USB Data I/O (D+)
High-Speed USB 2.0
USB instead of Auxiliary UART
30
GND
Ground
GND
Ground
31
RSVD / EXT32K
Reserved / 32 kHz Input
RSVD
Reserved
No functional difference
32
GND
Ground
GND
Ground
33
RSVD
Reserved
RSVD
Reserved
No functional difference
34
I2S_WA / RSVD
I
2
S Word Alignment / Reserved
1.8 V, Driver strength: 6 mA
I2S_WA
I
2
S Word Alignment
1.8 V, Driver strength: 2 mA
No functional difference
35
I2S_TXD / RSVD
I
2
S Data Output / Reserved
1.8 V, Driver strength: 5 mA
I2S_TXD
I
2
S Data Output
1.8 V, Driver strength: 2 mA
No functional difference
36
I2S_CLK / RSVD
I
2
S Clock / Reserved
1.8 V, Driver strength: 5 mA
I2S_CLK
I
2
S Clock
1.8 V, Driver strength: 2 mA
No functional difference
37
I2S_RXD / RSVD
I
2
S Data Input / Reserved
1.8 V, Internal pull-down:~18 k
I2S_RXD
I
2
S Data Input
1.8 V, Inner pull-down: ~9 k
No functional difference
38
SIM_CLK
SIM Clock Output
SIM_CLK
SIM Clock Output
No functional difference
39
SIM_IO
SIM Data I/O
SIM_IO
SIM Data I/O
No functional difference
40
SIM_RST
SIM Reset Output
SIM_RST
SIM Reset Output
No functional difference
41
VSIM
SIM Supply Output
VSIM
SIM Supply Output
No functional difference
42
SIM_DET
SIM Detection Input
1.8 V, Internal pull-down:~18 k
SIM_DET
SIM Detection Input
1.8 V, Inner pull-down: ~9 k
No functional difference
43
GND
Ground
GND
Ground
44
SPK_P / RSVD
Analog Audio Out (+) / Reserved
RSVD
Reserved
Analog audio not supported
45
SPK_N / RSVD
Analog Audio Out (-) / Reserved
RSVD
Reserved
Analog audio not supported
46
MIC_BIAS / RSVD
Microphone Supply Out / Reserved
RSVD
Reserved
Analog audio not supported
47
MIC_GND / RSVD
Microphone Ground / Reserved
RSVD
Reserved
Analog audio not supported
48
MIC_N / RSVD
Analog Audio In (-) / Reserved
RSVD
Reserved
Analog audio not supported
49
MIC_P / RSVD
Analog Audio In (+) / Reserved
RSVD
Reserved
Analog audio not supported
50
GND
Ground
GND
Ground
51-53
VCC
Module Supply Input
Normal op. range:
3.35 V – 4.5 V
Extended op. range:
3.00 V – 4.5 V
VCC
Module Supply Input
Normal op. range:
3.3 V – 4.4 V
Extended op. range:
3.1 V – 4.5 V
No functional difference
54-55
GND
Ground
GND
Ground
56
ANT
RF Antenna I/O
ESD immunity (IEC 61000-4-2):
±4 kV contact / ±8 kV air ESD
ANT
RF Antenna I/O
ESD immunity (IEC 61000-4-2):
±2 kV contact / ±4 kV air ESD
No functional difference
57-61
GND
Ground
GND
Ground
62
ANT_DET / RSVD
Antenna Detection Input / Reserved
ANT_DET
Antenna Detection Input
No functional difference
63-96
GND
Ground
GND
Ground
Table 53: SARA-G3 and SARA-U2 pin assignment with remarks for migration
For the detailed functional description of each interface of SARA-G3 and SARA-U2 series modules see the
related section in the section 1, whereas for detailed design-in see the related section in the chapter 2.
For the detailed electrical characteristics of each interface of SARA-G3 and SARA-U2 series modules see the
SARA-G3 series Data Sheet [1] and the SARA-U2 series Data Sheet [2].