User's Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.6 System function interfaces
- 1.7 Antenna interface
- 1.8 SIM interface
- 1.9 Serial interfaces
- 1.9.1 Asynchronous serial interface (UART)
- 1.9.1.1 UART features
- 1.9.1.2 UART AT interface configuration
- 1.9.1.3 UART signal behavior
- 1.9.1.4 UART and power-saving
- AT+UPSV=0: power saving disabled, fixed active-mode
- AT+UPSV=1: power saving enabled, cyclic idle/active-mode
- AT+UPSV=2: power saving enabled and controlled by the RTS line
- AT+UPSV=3: power saving enabled and controlled by the DTR line
- Wake up via data reception
- Additional considerations for SARA-U2 modules
- 1.9.1.5 Multiplexer protocol (3GPP 27.010)
- 1.9.2 Auxiliary asynchronous serial interface (UART AUX)
- 1.9.3 USB interface
- 1.9.4 DDC (I2C) interface
- 1.9.1 Asynchronous serial interface (UART)
- 1.10 Audio interface
- 1.11 General Purpose Input/Output (GPIO)
- 1.12 Reserved pins (RSVD)
- 1.13 System features
- 1.13.1 Network indication
- 1.13.2 Antenna detection
- 1.13.3 Jamming detection
- 1.13.4 TCP/IP and UDP/IP
- 1.13.5 FTP
- 1.13.6 HTTP
- 1.13.7 SMTP
- 1.13.8 SSL
- 1.13.9 Dual stack IPv4/IPv6
- 1.13.10 Smart temperature management
- 1.13.11 AssistNow clients and GNSS integration
- 1.13.12 Hybrid positioning and CellLocateTM
- 1.13.13 Firmware upgrade Over AT (FOAT)
- 1.13.14 Firmware upgrade Over The Air (FOTA)
- 1.13.15 In-Band modem (eCall / ERA-GLONASS)
- 1.13.16 SIM Access Profile (SAP)
- 1.13.17 Power saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a Low Drop-Out (LDO) linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable Li-Ion or Li-Pol battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for external battery charging circuit
- 2.2.1.8 Guidelines for external battery charging and power path management circuit
- 2.2.1.9 Guidelines for VCC supply layout design
- 2.2.1.10 Guidelines for grounding layout design
- 2.2.2 RTC supply (V_BCKP)
- 2.2.3 Interface supply (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interface
- 2.6 Serial interfaces
- 2.6.1 Asynchronous serial interface (UART)
- 2.6.1.1 Guidelines for UART circuit design
- Providing the full RS-232 functionality (using the complete V.24 link)
- Providing the TXD, RXD, RTS, CTS and DTR lines only (not using the complete V.24 link)
- Providing the TXD, RXD, RTS and CTS lines only (not using the complete V.24 link)
- Providing the TXD and RXD lines only (not using the complete V24 link)
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 Auxiliary asynchronous serial interface (UART AUX)
- 2.6.3 Universal Serial Bus (USB)
- 2.6.4 DDC (I2C) interface
- 2.6.1 Asynchronous serial interface (UART)
- 2.7 Audio interface
- 2.7.1 Analog audio interface
- 2.7.1.1 Guidelines for microphone and speaker connection circuit design (headset / handset modes)
- 2.7.1.2 Guidelines for microphone and loudspeaker connection circuit design (hands-free mode)
- 2.7.1.3 Guidelines for external analog audio device connection circuit design
- 2.7.1.4 Guidelines for analog audio layout design
- 2.7.2 Digital audio interface
- 2.7.1 Analog audio interface
- 2.8 General Purpose Input/Output (GPIO)
- 2.9 Reserved pins (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Thermal guidelines
- 2.13 ESD guidelines
- 2.14 SARA-G350 ATEX integration in explosive atmospheres applications
- 2.15 Schematic for SARA-G3 and SARA-U2 series module integration
- 2.16 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between LISA and SARA-G3 modules
- A.1 Overview
- A.2 Checklist for migration
- A.3 Software migration
- A.4 Hardware migration
- B Migration between SARA-G3 and SARA-U2
- C Glossary
- Related documents
- Revision history
- Contact
SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R08 Objective Specification Appendix
Page 175 of 188
A.4.9 Pin-out comparison between LISA and SARA-G3
Table 51 summarizes the pin electrical differences between LISA and SARA-G3 cellular modules.
Pin Name
N°
SARA-G3 series
N°
LISA-C2 series
LISA-U1 series
LISA-U2 series
Power
VCC
51-53
Normal op. range:
3.35 V – 4.5 V
Extended op. range:
3.00 V – 4.5 V
High pulse current
due to GSM TDMA
61-63
Normal op. range:
3.3 V – 4.4 V
Extended op. range:
Not applicable
No high pulse current
due to CDMA
Normal op. range:
3.4 V – 4.2 V
Extended op. range:
3.1 V – 4.2 V
High pulse current
due to GSM TDMA
Normal op. range:
3.3 V – 4.4 V
Extended op. range:
3.1 V – 4.5 V
High pulse current
due to GSM TDMA
V_BCKP
2
Output characteristics:
2.3 V typ, 2 mA max
Input op. range:
1.0 V – 2.4 V
2
Not Available
Output characteristics:
2.3 V typ, 3 mA max
Input op. range:
1.0 V – 2.5 V
Output characteristics:
1.8 V typ, 3 mA max
Input op. range:
1.0 V – 1.9 V
V_INT
4
Output characteristics:
1.8 V typ, 50 mA max
4
Output characteristics:
1.8 V typ, 50 mA max
Output characteristics:
1.8 V typ, 50 mA max
Output characteristics:
1.8 V typ, 50 mA max
Antenna
ANT
56
RF input/output for Tx/Rx
antenna
68
RF input/output for
Tx/Rx antenna
RF input/output for
Tx/Rx antenna
RF input/output for
main Tx/Rx antenna
ANT_DIV
Not Available
74
Not Available
Not Available
LISA-U230 only:
RF input for
Rx diversity antenna
ANT_DET
62
SARA-G340/SARA-G350:
Input for antenna
detection circuit
Not Available
Internal antenna
detection circuit
Internal antenna
detection circuit
System
PWR_ON
15
No internal pull-up
L-level: -0.10 V – 0.65 V
H-level: 2.00 V – 4.50 V
ON L-level time:
5 ms min
OFF L-level pulse time:
Not Available
19
180 k internal pull-up
L-level: -0.30 V – 0.30 V
H-level: 2.00 V – 4.70 V
ON L-level pulse time:
150 ms min
OFF L-level pulse time:
Not Available
No internal pull-up
L-level: -0.30 V –0.65 V
H-level: 2.00 V – 4.50 V
ON L-level pulse time:
5 ms min
OFF L-level pulse time:
Not Available
No internal pull-up
L-level: -0.30 V – 0.65 V
H-level: 1.50 V – 4.40 V
ON L-level pulse time:
50 µs min / 80 µs max
OFF L-level pulse time:
1 s min
RESET_N
18
Internal diode & pull-up
L-level: -0.30 V – 0.30 V
H-level: 2.00 V – 4.70 V
Reset L-level pulse time:
SARA-G340/SARA-G350:
50 ms min
SARA-G300/SARA-G310:
3 s min
22
550 internal pull-up
L-level: -0.30 V – 0.63 V
H-level: 1.32 V – 2.10 V
Reset L-level pulse time:
300 ms min
10 k internal pull-up
L-level: -0.30 V – 0.65 V
H-level: 1.69 V – 2.48 V
Reset L-level pulse time:
50 ms min
10 k internal pull-up
L-level: -0.30 V – 0.51 V
H-level: 1.32 V – 2.01 V
Reset L-level pulse time:
50 ms min
EXT32K
31
SARA-G300/SARA-G310:
32 kHz input for RTC
& low power idle mode
SARA-G340/SARA-G350:
Not Available:
Internal 32 kHz for RTC
& low power idle mode
Not Available:
Internal reference for
low power idle mode
Not Available:
Internal 32 kHz for RTC
& low power idle mode
Not Available:
Internal 32 kHz for RTC
& low power idle mode
32K_OUT
24
SARA-G300/SARA-G310:
32 kHz output, only to
feed the EXT32K input
SARA-G340/SARA-G350:
Not Available
Not Available
Not Available
Not Available