User's Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.6 System function interfaces
- 1.7 Antenna interface
- 1.8 SIM interface
- 1.9 Serial interfaces
- 1.9.1 Asynchronous serial interface (UART)
- 1.9.1.1 UART features
- 1.9.1.2 UART AT interface configuration
- 1.9.1.3 UART signal behavior
- 1.9.1.4 UART and power-saving
- AT+UPSV=0: power saving disabled, fixed active-mode
- AT+UPSV=1: power saving enabled, cyclic idle/active-mode
- AT+UPSV=2: power saving enabled and controlled by the RTS line
- AT+UPSV=3: power saving enabled and controlled by the DTR line
- Wake up via data reception
- Additional considerations for SARA-U2 modules
- 1.9.1.5 Multiplexer protocol (3GPP 27.010)
- 1.9.2 Auxiliary asynchronous serial interface (UART AUX)
- 1.9.3 USB interface
- 1.9.4 DDC (I2C) interface
- 1.9.1 Asynchronous serial interface (UART)
- 1.10 Audio interface
- 1.11 General Purpose Input/Output (GPIO)
- 1.12 Reserved pins (RSVD)
- 1.13 System features
- 1.13.1 Network indication
- 1.13.2 Antenna detection
- 1.13.3 Jamming detection
- 1.13.4 TCP/IP and UDP/IP
- 1.13.5 FTP
- 1.13.6 HTTP
- 1.13.7 SMTP
- 1.13.8 SSL
- 1.13.9 Dual stack IPv4/IPv6
- 1.13.10 Smart temperature management
- 1.13.11 AssistNow clients and GNSS integration
- 1.13.12 Hybrid positioning and CellLocateTM
- 1.13.13 Firmware upgrade Over AT (FOAT)
- 1.13.14 Firmware upgrade Over The Air (FOTA)
- 1.13.15 In-Band modem (eCall / ERA-GLONASS)
- 1.13.16 SIM Access Profile (SAP)
- 1.13.17 Power saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a Low Drop-Out (LDO) linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable Li-Ion or Li-Pol battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for external battery charging circuit
- 2.2.1.8 Guidelines for external battery charging and power path management circuit
- 2.2.1.9 Guidelines for VCC supply layout design
- 2.2.1.10 Guidelines for grounding layout design
- 2.2.2 RTC supply (V_BCKP)
- 2.2.3 Interface supply (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interface
- 2.6 Serial interfaces
- 2.6.1 Asynchronous serial interface (UART)
- 2.6.1.1 Guidelines for UART circuit design
- Providing the full RS-232 functionality (using the complete V.24 link)
- Providing the TXD, RXD, RTS, CTS and DTR lines only (not using the complete V.24 link)
- Providing the TXD, RXD, RTS and CTS lines only (not using the complete V.24 link)
- Providing the TXD and RXD lines only (not using the complete V24 link)
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 Auxiliary asynchronous serial interface (UART AUX)
- 2.6.3 Universal Serial Bus (USB)
- 2.6.4 DDC (I2C) interface
- 2.6.1 Asynchronous serial interface (UART)
- 2.7 Audio interface
- 2.7.1 Analog audio interface
- 2.7.1.1 Guidelines for microphone and speaker connection circuit design (headset / handset modes)
- 2.7.1.2 Guidelines for microphone and loudspeaker connection circuit design (hands-free mode)
- 2.7.1.3 Guidelines for external analog audio device connection circuit design
- 2.7.1.4 Guidelines for analog audio layout design
- 2.7.2 Digital audio interface
- 2.7.1 Analog audio interface
- 2.8 General Purpose Input/Output (GPIO)
- 2.9 Reserved pins (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Thermal guidelines
- 2.13 ESD guidelines
- 2.14 SARA-G350 ATEX integration in explosive atmospheres applications
- 2.15 Schematic for SARA-G3 and SARA-U2 series module integration
- 2.16 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between LISA and SARA-G3 modules
- A.1 Overview
- A.2 Checklist for migration
- A.3 Software migration
- A.4 Hardware migration
- B Migration between SARA-G3 and SARA-U2
- C Glossary
- Related documents
- Revision history
- Contact
SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R08 Objective Specification Appendix
Page 168 of 188
Appendix
A Migration between LISA and SARA-G3 modules
A.1 Overview
Migrating between LISA-U1, LISA-U2, LISA-C2 series and SARA-G3 series module designs is a straight-forward
procedure that allows customers to take maximum advantage of their hardware and software investments.
The SARA cellular modules (26.0 x 16.0 mm LGA) have a different form factor than the LISA cellular modules
(33.2 x 22.4 mm LCC), but the footprint of SARA and LISA modules has been developed to provide pin-to-pin
compatibility on the lateral edge of the antenna pin so that each SARA / LISA pin can share the same pad on the
application board, due to the same pitch and nearly the same functions provided, as described in Figure 90.
64 63 61 60 58 57 55 54
22 23 25 26 28 29 31 32
11
10
8
7
5
4
2
1
21
19
18
16
15
13
12
43
44
46
47
49
50
52
53
33
35
36
38
39
41
42
65 66 67 68 69 70
71 72 73 74 75 76
77 78
79 80
81 82
83 84
85 86 87 88 89 90
91 92 93 94 95 96
CTS
RTS
DCD
RI
V_INT
V_BCKP
GND
RSVD
RESET_N
RSVD/ GPIO1
PWR_ON
RXD
TXD
3
20
17
14
9
6
24 27 30
51
48
45
40
37
34
5962 56
GND
GND
DSR
DTR
GND
RSVD
GND
GND
RXD_AUX
TXD_AUX
EXT32 / RSVD
GND
RSVD/ GPIO2
32K_OUT/GPIO3
RSVD/ SDA
RSVD/ SCL
RSVD/ GPIO4
GND
GND
GND
RSVD/ SPK_P
RSVD/ MIC_BIAS
RSVD/ MIC_GND
RSVD/ MIC_P
GND
VCC
VCC
RSVD
RSVD/ I2S_TXD
RSVD/ I2S_CLK
SIM_CLK
SIM_IO
VSIM
SIM_DET
VCC
RSVD/ MIC_N
RSVD/ SPK_N
SIM_RST
RSVD/ I2S_RXD
RSVD/ I2S_WA
GND
GND
GND
GND
GND
GND
GND
GND
GND
RSVD/ ANT_DET
ANT
SARA-G3 series
Top View
Pin 65-96: GND
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
GND
VCC
VCC
VCC
GND
SPI_MRDY
SPI_SRDY
SPI_MISO
SPI_MOSI
SPI_SCLK
RSVD / SPK_N
GND
RSVD / SPK_P
RSVD
GPIO5
VSIM
SIM_RST
SIM_IO
SIM_CLK
SDA
SCL
RSVD / I2S_RXD
RSVD / I2S_CLK
RSVD / I2S_TXD
RSVD / I2S_WA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
V_BCKP
GND
V_INT
RSVD
GND
GND
GND
DSR
RI
DCD
DTR
GND
RTS
CTS
TXD
RXD
GND
VUSB_DET
PWR_ON
GPIO1
GPIO2
RESET_N
GPIO3
GPIO4
GND
26
27
USB_D-
USB_D+
40
39
RSVD / MIC_P
RSVD / MIC_N
28 29 30 31 32 33 34 35 36 37 38
76 75 74 73 72 71 70 69 68 67 66
LISA-U1 series
Top View
GND
RSVD
GND
GND
GND
GND
GND
ANT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
GND
VCC
VCC
VCC
GND
SPI_MRDY / GPIO14
SPI_SRDY / GPIO13
SPI_MISO / GPIO12
SPI_MOSI / GPIO11
SPI_SCLK / GPIO10
GPIO9 / I2S1_WA
GND
GPIO8 / I2S1_CLK
RSVD / CODEC_CLK
GPIO5
VSIM
SIM_RST
SIM_IO
SIM_CLK
SDA
SCL
RSVD / I2S_RXD
RSVD / I2S_CLK
RSVD / I2S_TXD
RSVD / I2S_WA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
V_BCKP
GND
V_INT
RSVD
GND
GND
GND
DSR
RI
DCD
DTR
GND
RTS
CTS
TXD
RXD
GND
VUSB_DET
PWR_ON
GPIO1
GPIO2
RESET_N
GPIO3
GPIO4
GND
26
27
USB_D-
USB_D+
40
39
GPIO7 / I2S1_TXD
GPIO6 / I2S1_RXD
28 29 30 31 32 33 34 35 36 37 38
76 75 74 73 72 71 70 69 68 67 66
LISA-U2 series
Top View
GND
RSVD/ ANT_DIV
GND
GND
GND
GND
GND
ANT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
GND
VCC
VCC
VCC
GND
RSVD
RSVD
RSVD
RSVD
RSVD
SPK_N
GND
SPK_P
RSVD
GPIO5
VSIM
SIM_RST
SIM_IO
SIM_CLK
RSVD
RSVD
PCM_DI
PCM_CLK
PCM_DO
PCM_SYNC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
RSVD
GND
V_INT
RSVD
GND
GND
GND
RSVD
RI
RSVD
RSVD
GND
RTS
CTS
TXD
RXD
GND
VUSB_DET
PWR_ON
GPIO1
GPIO2
RESET_N
GPIO3
GPIO4
GND
26
27
USB_D-
USB_D+
40
39
MIC_P
MIC_N
28 29 30 31 32 33 34 35 36 37 38
76 75 74 73 72 71 70 69 68 67 66
LISA-C2 series
Top View
GND
RSVD
GND
GND
GND
GND
GND
ANT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Figure 90: LISA series vs. SARA-G3 series modules pin assignment: highlighted pads that can be shared on the application board
This is the basis of the Nested Design concept: any SARA-G3, LISA-U1, LISA-U2, or LISA-C2 module can be
mounted on the same nested board as shown in Figure 91, enabling straightforward development of products
supporting either GSM/GPRS, W-CDMA or CDMA cellular technology with the same application board.
LISA
NESTED APPLICATION BOARD
Top Layer and Solder Mask
LISA mounting option
with LISA Paste Mask
SARA
SARA mounting option
with SARA Paste Mask
ANT pad
Figure 91: Nested Design concept description: LISA and SARA modules alternatively mounted on the same application board