User's Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.6 System function interfaces
- 1.7 Antenna interface
- 1.8 SIM interface
- 1.9 Serial interfaces
- 1.9.1 Asynchronous serial interface (UART)
- 1.9.1.1 UART features
- 1.9.1.2 UART AT interface configuration
- 1.9.1.3 UART signal behavior
- 1.9.1.4 UART and power-saving
- AT+UPSV=0: power saving disabled, fixed active-mode
- AT+UPSV=1: power saving enabled, cyclic idle/active-mode
- AT+UPSV=2: power saving enabled and controlled by the RTS line
- AT+UPSV=3: power saving enabled and controlled by the DTR line
- Wake up via data reception
- Additional considerations for SARA-U2 modules
- 1.9.1.5 Multiplexer protocol (3GPP 27.010)
- 1.9.2 Auxiliary asynchronous serial interface (UART AUX)
- 1.9.3 USB interface
- 1.9.4 DDC (I2C) interface
- 1.9.1 Asynchronous serial interface (UART)
- 1.10 Audio interface
- 1.11 General Purpose Input/Output (GPIO)
- 1.12 Reserved pins (RSVD)
- 1.13 System features
- 1.13.1 Network indication
- 1.13.2 Antenna detection
- 1.13.3 Jamming detection
- 1.13.4 TCP/IP and UDP/IP
- 1.13.5 FTP
- 1.13.6 HTTP
- 1.13.7 SMTP
- 1.13.8 SSL
- 1.13.9 Dual stack IPv4/IPv6
- 1.13.10 Smart temperature management
- 1.13.11 AssistNow clients and GNSS integration
- 1.13.12 Hybrid positioning and CellLocateTM
- 1.13.13 Firmware upgrade Over AT (FOAT)
- 1.13.14 Firmware upgrade Over The Air (FOTA)
- 1.13.15 In-Band modem (eCall / ERA-GLONASS)
- 1.13.16 SIM Access Profile (SAP)
- 1.13.17 Power saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a Low Drop-Out (LDO) linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable Li-Ion or Li-Pol battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for external battery charging circuit
- 2.2.1.8 Guidelines for external battery charging and power path management circuit
- 2.2.1.9 Guidelines for VCC supply layout design
- 2.2.1.10 Guidelines for grounding layout design
- 2.2.2 RTC supply (V_BCKP)
- 2.2.3 Interface supply (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interface
- 2.6 Serial interfaces
- 2.6.1 Asynchronous serial interface (UART)
- 2.6.1.1 Guidelines for UART circuit design
- Providing the full RS-232 functionality (using the complete V.24 link)
- Providing the TXD, RXD, RTS, CTS and DTR lines only (not using the complete V.24 link)
- Providing the TXD, RXD, RTS and CTS lines only (not using the complete V.24 link)
- Providing the TXD and RXD lines only (not using the complete V24 link)
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 Auxiliary asynchronous serial interface (UART AUX)
- 2.6.3 Universal Serial Bus (USB)
- 2.6.4 DDC (I2C) interface
- 2.6.1 Asynchronous serial interface (UART)
- 2.7 Audio interface
- 2.7.1 Analog audio interface
- 2.7.1.1 Guidelines for microphone and speaker connection circuit design (headset / handset modes)
- 2.7.1.2 Guidelines for microphone and loudspeaker connection circuit design (hands-free mode)
- 2.7.1.3 Guidelines for external analog audio device connection circuit design
- 2.7.1.4 Guidelines for analog audio layout design
- 2.7.2 Digital audio interface
- 2.7.1 Analog audio interface
- 2.8 General Purpose Input/Output (GPIO)
- 2.9 Reserved pins (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Thermal guidelines
- 2.13 ESD guidelines
- 2.14 SARA-G350 ATEX integration in explosive atmospheres applications
- 2.15 Schematic for SARA-G3 and SARA-U2 series module integration
- 2.16 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between LISA and SARA-G3 modules
- A.1 Overview
- A.2 Checklist for migration
- A.3 Software migration
- A.4 Hardware migration
- B Migration between SARA-G3 and SARA-U2
- C Glossary
- Related documents
- Revision history
- Contact
SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R08 Objective Specification Design-in
Page 144 of 188
Table 48 reports the u-blox SARA-G3 and SARA-U2 reference designs ESD immunity test results, according to
the CENELEC EN 61000-4-2 [18], ETSI EN 301 489-1 [19], 301 489-7 [20], 301 489-24 [21] test requirements.
Category
Application
Immunity Level
Remarks
Contact Discharge
to coupling planes
(indirect contact discharge)
Enclosure
+4 kV / –4 kV
Contact Discharges
to conducted surfaces
(direct contact discharge)
Enclosure port
Not Applicable
Test not applicable to u-blox reference design because it
does not provide enclosure surface.
The test is applicable only to equipments providing
conductive enclosure surface.
Antenna port
+4 kV / –4 kV
Test applicable to u-blox reference design because it
provides antenna with conductive & insulating surfaces.
The test is applicable only to equipments providing
antenna with conductive surface.
Air Discharge
at insulating surfaces
Enclosure port
Not Applicable
Test not applicable to the u-blox reference design
because it does not provide an enclosure surface.
The test is applicable only to equipments providing
insulating enclosure surface.
Antenna port
+8 kV / –8 kV
Test applicable to u-blox reference design because it
provides antenna with conductive & insulating surfaces.
The test is applicable only to equipments providing
antenna with insulating surface.
Table 48: Enclosure ESD immunity level of u-blox SARA-G3 and SARA-U2 reference designs
SARA-G3 and SARA-U2 reference designs implement all the ESD precautions described in section 2.13.3.
2.13.3 ESD application circuits
The application circuits described in this section are recommended and should be implemented in any device
that integrates a SARA-G3 and SARA-U2 series module, according to the application board classification (see
ETSI EN 301 489-1 [19]), to satisfy the requirements for ESD immunity test summarized in Table 47.
Antenna interface
The ANT pin of SARA-G3 modules provides ESD immunity up to ±4 kV for direct Contact Discharge and up to
±8 kV for Air Discharge according to IEC 61000-4-2: no further precaution to ESD immunity test is needed, as
implemented in the EMC / ESD approved reference design of SARA-G3 modules.
The ANT pin of SARA-U2 modules provides ESD immunity up to ±2 kV for direct Contact Discharge and up to
±4 kV for Air Discharge according to IEC 61000-4-2: higher protection level is required if the line is externally
accessible on the device (i.e. the application board where the SARA-U2 module is mounted).
The following precautions are suggested for satisfying ESD immunity test requirements using SARA-U2 modules:
If the device implements an embedded antenna, the device insulating enclosure should provide protection to
direct contact discharge up to ±4 kV and protection to air discharge up to ±8 kV to the antenna interface
If the device implements an external antenna, the antenna and its connecting cable should provide a
completely insulated enclosure able to provide protection to direct contact discharge up to ±4 kV and
protection to air discharge up to ±8 kV to the whole antenna and cable surfaces
If the device implements an external antenna, and the antenna and its connecting cable do not provide a
completely insulated enclosure able to provide protection to direct contact discharge up to ±4 kV and
protection to air discharge up to ±8 kV to the whole antenna and cable surfaces, an external high pass filter,
consisting of a series 15 pF capacitor (Murata GRM1555C1H150JA01) and a shunt 39 nH coil (Murata