User's Manual

SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R08 Objective Specification System description
Page 14 of 188
Function
Pin Name
Module
Pin No
I/O
Description
Remarks
SIM
VSIM
All
41
O
SIM supply output
VSIM = 1.80 V typ. or 2.85 V typ. automatically
generated according to the connected SIM type.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_IO
All
39
I/O
SIM data
Data input/output for 1.8 V / 3 V SIM
Internal 4.7 k pull-up to VSIM.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_CLK
All
38
O
SIM clock
3.25 MHz clock output for 1.8 V / 3 V SIM
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_RST
All
40
O
SIM reset
Reset output for 1.8 V / 3 V SIM
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_DET
All
42
I /
I/O
SIM detection /
GPIO
1.8 V input for SIM presence detection function.
Pin configurable also as GPIO on SARA-U2 series.
See section 1.8.2 for functional description.
See section 2.5 for external circuit design-in.
UART
RXD
All
13
O
UART data output
1.8 V output, Circuit 104 (RXD) in ITU-T V.24,
for AT, data, FOAT on SARA-G3 series modules,
for AT, data, FOAT, FW upgrade via EasyFlash tool
and diagnostic on SARA-U2 series modules.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
TXD
All
12
I
UART data input
1.8 V input, Circuit 103 (TXD) in ITU-T V.24,
for AT, data, FOAT on SARA-G3 series modules,
for AT, data, FOAT, FW upgrade via EasyFlash tool
and diagnostic on SARA-U2 series modules.
Internal active pull-up to V_INT.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
CTS
All
11
O
UART clear to
send output
1.8 V output, Circuit 106 (CTS) in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
RTS
All
10
I
UART ready to
send input
1.8 V input, Circuit 105 (RTS) in ITU-T V.24.
Internal active pull-up to V_INT.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
DSR
All
6
O
UART data set
ready output
1.8 V output, Circuit 107 (DSR) in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
RI
All
7
O
UART ring
indicator output
1.8 V output, Circuit 125 (RI) in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
DTR
All
9
I
UART data
terminal ready
input
1.8 V input, Circuit 108/2 (DTR) in ITU-T V.24.
Internal active pull-up to V_INT.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
DCD
All
8
O
UART data carrier
detect output
1.8 V input, Circuit 109 (DCD) in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.