User's Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.6 System function interfaces
- 1.7 Antenna interface
- 1.8 SIM interface
- 1.9 Serial interfaces
- 1.9.1 Asynchronous serial interface (UART)
- 1.9.1.1 UART features
- 1.9.1.2 UART AT interface configuration
- 1.9.1.3 UART signal behavior
- 1.9.1.4 UART and power-saving
- AT+UPSV=0: power saving disabled, fixed active-mode
- AT+UPSV=1: power saving enabled, cyclic idle/active-mode
- AT+UPSV=2: power saving enabled and controlled by the RTS line
- AT+UPSV=3: power saving enabled and controlled by the DTR line
- Wake up via data reception
- Additional considerations for SARA-U2 modules
- 1.9.1.5 Multiplexer protocol (3GPP 27.010)
- 1.9.2 Auxiliary asynchronous serial interface (UART AUX)
- 1.9.3 USB interface
- 1.9.4 DDC (I2C) interface
- 1.9.1 Asynchronous serial interface (UART)
- 1.10 Audio interface
- 1.11 General Purpose Input/Output (GPIO)
- 1.12 Reserved pins (RSVD)
- 1.13 System features
- 1.13.1 Network indication
- 1.13.2 Antenna detection
- 1.13.3 Jamming detection
- 1.13.4 TCP/IP and UDP/IP
- 1.13.5 FTP
- 1.13.6 HTTP
- 1.13.7 SMTP
- 1.13.8 SSL
- 1.13.9 Dual stack IPv4/IPv6
- 1.13.10 Smart temperature management
- 1.13.11 AssistNow clients and GNSS integration
- 1.13.12 Hybrid positioning and CellLocateTM
- 1.13.13 Firmware upgrade Over AT (FOAT)
- 1.13.14 Firmware upgrade Over The Air (FOTA)
- 1.13.15 In-Band modem (eCall / ERA-GLONASS)
- 1.13.16 SIM Access Profile (SAP)
- 1.13.17 Power saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a Low Drop-Out (LDO) linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable Li-Ion or Li-Pol battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for external battery charging circuit
- 2.2.1.8 Guidelines for external battery charging and power path management circuit
- 2.2.1.9 Guidelines for VCC supply layout design
- 2.2.1.10 Guidelines for grounding layout design
- 2.2.2 RTC supply (V_BCKP)
- 2.2.3 Interface supply (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interface
- 2.6 Serial interfaces
- 2.6.1 Asynchronous serial interface (UART)
- 2.6.1.1 Guidelines for UART circuit design
- Providing the full RS-232 functionality (using the complete V.24 link)
- Providing the TXD, RXD, RTS, CTS and DTR lines only (not using the complete V.24 link)
- Providing the TXD, RXD, RTS and CTS lines only (not using the complete V.24 link)
- Providing the TXD and RXD lines only (not using the complete V24 link)
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 Auxiliary asynchronous serial interface (UART AUX)
- 2.6.3 Universal Serial Bus (USB)
- 2.6.4 DDC (I2C) interface
- 2.6.1 Asynchronous serial interface (UART)
- 2.7 Audio interface
- 2.7.1 Analog audio interface
- 2.7.1.1 Guidelines for microphone and speaker connection circuit design (headset / handset modes)
- 2.7.1.2 Guidelines for microphone and loudspeaker connection circuit design (hands-free mode)
- 2.7.1.3 Guidelines for external analog audio device connection circuit design
- 2.7.1.4 Guidelines for analog audio layout design
- 2.7.2 Digital audio interface
- 2.7.1 Analog audio interface
- 2.8 General Purpose Input/Output (GPIO)
- 2.9 Reserved pins (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Thermal guidelines
- 2.13 ESD guidelines
- 2.14 SARA-G350 ATEX integration in explosive atmospheres applications
- 2.15 Schematic for SARA-G3 and SARA-U2 series module integration
- 2.16 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between LISA and SARA-G3 modules
- A.1 Overview
- A.2 Checklist for migration
- A.3 Software migration
- A.4 Hardware migration
- B Migration between SARA-G3 and SARA-U2
- C Glossary
- Related documents
- Revision history
- Contact
SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R08 Objective Specification Design-in
Page 133 of 188
2.7.1.3 Guidelines for external analog audio device connection circuit design
The differential analog audio I/O can be used to connect the module to an external analog audio device. Audio
devices with a differential analog I/O are preferable, as they are more immune to external disturbances.
Figure 77 and Table 43 describe the application circuits, following the suggested circuit design-in.
Guidelines for the connection to a differential analog audio input:
The SPK_P / SPK_N balanced output of the module must be connected to the differential input of the
external audio device by means of series capacitors for DC blocking (e.g. 10 µF) to decouple the bias present
at the module output, as described in the left side of Figure 77
Guidelines for the connection to a single ended analog audio input:
A proper differential to single ended circuit must be inserted from the SPK_P / SPK_N balanced output of
the module to the single ended input of the external audio device, as described in the Figure 77 right side:
10 µF series capacitors are provided to decouple the bias present at the module output, and a voltage
divider is provided to properly adapt the signal level from module output to external audio device input
Guidelines for the connection to a differential analog audio output:
The MIC_P / MIC_N balanced input of the module must be connected to the differential output of the
external audio device by means of series capacitors for DC blocking (e.g. 10 µF) to decouple the bias present
at the module input, as described in the Figure 77 left side
Guidelines for the connection to a single ended analog audio output:
A proper single ended to differential circuit has to be inserted from the single ended output of the external
audio device to the MIC_P / MIC_N balanced input of the module, as described in the Figure 77 right side:
10 µF series capacitors are provided to decouple the bias present at the module input, and a voltage divider
is provided to properly adapt the signal level from the external audio device output to the module input
Additional guidelines for any connection:
The DC-block series capacitor acts as high-pass filter for audio signals, with cut-off frequency depending on
both the values of capacitor and on the input impedance of the device. For example: in case of differential
input impedance of 600 , the two 10 µF capacitors will set the -3 dB cut-off frequency to 53 Hz, while for
single ended connection to 600 external device, the cut-off frequency with just the single 10 µF capacitor
will be 103 Hz. In both cases the high-pass filter has a low enough cut-off for proper frequency response
Use a suitable power-on sequence to avoid audio bump due to charging of the capacitor: the final audio
stage should be always enabled as last one
The signal levels can be adapted by setting gain using AT commands (see u-blox AT Commands Manual [3],
+USGC, +UMGC), but additional circuitry must be inserted if SPK_P / SPK_N output level of the module is
too high for the audio device input or if the audio device output level is too high for MIC_P / MIC_N, as the
voltage dividers present in the circuits described in the Figure 77 right side to properly adapt the signal level
SARA-G340
SARA-G350
C1
C2
45
SPK_N
44
SPK_P
GND
49
MIC_P
GND
Analog IN (-)
Analog IN (+)
Analog OUT (-)
Analog OUT (+)
Audio Device
GND
GND
48
MIC_N
C3
C4
SARA-G340
SARA-G350
45
SPK_N
44
SPK_P
GND
49
MIC_P
GND
Analog IN
Audio Device
GND
Reference
48
MIC_N
Analog OUT
C5
C6
R2
R1
R4
R3
C7
C8
46
MIC_BIAS
47
MIC_GND
46
MIC_BIAS
47
MIC_GND
Figure 77: Application circuits to connect the module to audio devices with proper differential or single-ended input/output