User's Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.6 System function interfaces
- 1.7 Antenna interface
- 1.8 SIM interface
- 1.9 Serial interfaces
- 1.9.1 Asynchronous serial interface (UART)
- 1.9.1.1 UART features
- 1.9.1.2 UART AT interface configuration
- 1.9.1.3 UART signal behavior
- 1.9.1.4 UART and power-saving
- AT+UPSV=0: power saving disabled, fixed active-mode
- AT+UPSV=1: power saving enabled, cyclic idle/active-mode
- AT+UPSV=2: power saving enabled and controlled by the RTS line
- AT+UPSV=3: power saving enabled and controlled by the DTR line
- Wake up via data reception
- Additional considerations for SARA-U2 modules
- 1.9.1.5 Multiplexer protocol (3GPP 27.010)
- 1.9.2 Auxiliary asynchronous serial interface (UART AUX)
- 1.9.3 USB interface
- 1.9.4 DDC (I2C) interface
- 1.9.1 Asynchronous serial interface (UART)
- 1.10 Audio interface
- 1.11 General Purpose Input/Output (GPIO)
- 1.12 Reserved pins (RSVD)
- 1.13 System features
- 1.13.1 Network indication
- 1.13.2 Antenna detection
- 1.13.3 Jamming detection
- 1.13.4 TCP/IP and UDP/IP
- 1.13.5 FTP
- 1.13.6 HTTP
- 1.13.7 SMTP
- 1.13.8 SSL
- 1.13.9 Dual stack IPv4/IPv6
- 1.13.10 Smart temperature management
- 1.13.11 AssistNow clients and GNSS integration
- 1.13.12 Hybrid positioning and CellLocateTM
- 1.13.13 Firmware upgrade Over AT (FOAT)
- 1.13.14 Firmware upgrade Over The Air (FOTA)
- 1.13.15 In-Band modem (eCall / ERA-GLONASS)
- 1.13.16 SIM Access Profile (SAP)
- 1.13.17 Power saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a Low Drop-Out (LDO) linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable Li-Ion or Li-Pol battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for external battery charging circuit
- 2.2.1.8 Guidelines for external battery charging and power path management circuit
- 2.2.1.9 Guidelines for VCC supply layout design
- 2.2.1.10 Guidelines for grounding layout design
- 2.2.2 RTC supply (V_BCKP)
- 2.2.3 Interface supply (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interface
- 2.6 Serial interfaces
- 2.6.1 Asynchronous serial interface (UART)
- 2.6.1.1 Guidelines for UART circuit design
- Providing the full RS-232 functionality (using the complete V.24 link)
- Providing the TXD, RXD, RTS, CTS and DTR lines only (not using the complete V.24 link)
- Providing the TXD, RXD, RTS and CTS lines only (not using the complete V.24 link)
- Providing the TXD and RXD lines only (not using the complete V24 link)
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 Auxiliary asynchronous serial interface (UART AUX)
- 2.6.3 Universal Serial Bus (USB)
- 2.6.4 DDC (I2C) interface
- 2.6.1 Asynchronous serial interface (UART)
- 2.7 Audio interface
- 2.7.1 Analog audio interface
- 2.7.1.1 Guidelines for microphone and speaker connection circuit design (headset / handset modes)
- 2.7.1.2 Guidelines for microphone and loudspeaker connection circuit design (hands-free mode)
- 2.7.1.3 Guidelines for external analog audio device connection circuit design
- 2.7.1.4 Guidelines for analog audio layout design
- 2.7.2 Digital audio interface
- 2.7.1 Analog audio interface
- 2.8 General Purpose Input/Output (GPIO)
- 2.9 Reserved pins (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Thermal guidelines
- 2.13 ESD guidelines
- 2.14 SARA-G350 ATEX integration in explosive atmospheres applications
- 2.15 Schematic for SARA-G3 and SARA-U2 series module integration
- 2.16 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between LISA and SARA-G3 modules
- A.1 Overview
- A.2 Checklist for migration
- A.3 Software migration
- A.4 Hardware migration
- B Migration between SARA-G3 and SARA-U2
- C Glossary
- Related documents
- Revision history
- Contact
SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R08 Objective Specification Design-in
Page 131 of 188
2.7.1.2 Guidelines for microphone and loudspeaker connection circuit design (hands-free mode)
Figure 76 shows an application circuit for the analog audio interface in hands-free mode, connecting a 2.2 k
electret microphone and an 8 or 4 loudspeaker:
External microphone can be connected to the uplink path of the module, since the module provides supply
and reference as well as differential signal input for the external microphone
Using a 8 or 4 loudspeaker for the hands-free mode, an external audio amplifier must be provided on
the application board to amplify the low power audio signal provided by the downlink path of the module,
so that the external audio amplifier will drive the 8 or 4 loudspeaker, since differential analog audio
output of the module is able to directly drive loads with resistance rating greater than 14
As in the example circuit in Figure 76, follow the general guidelines for the design of an analog audio circuit for
hands-free mode:
Provide proper supply to the used electret microphone, providing a proper connection from the MIC_BIAS
supply output to the microphone. It is suggested to implement a bridge:
o The electret microphone, with its nominal intrinsic resistance value, represents one resistor of the
bridge.
o To achieve good supply noise rejection, the ratio of the two resistance in one leg (R2/R3) should be
equal to the ratio of the two resistance in the other leg (R4/MIC), i.e. R2 has to be equal to R4 (e.g.
2.2 k) and R3 must be equal to the microphone nominal intrinsic resistance value (e.g. 2.2 k).
Provide a series resistor at the MIC_BIAS supply output and then mount a good bypass capacitor to provide
additional supply noise filtering, as the R1 series resistor (2.2 k) and the C1 bypass capacitor (10 µF).
Do not place a bypass capacitor directly at the MIC_BIAS supply output, since proper internal bypass
capacitor is already provided to guarantee stable operation of the internal regulator.
Connect the reference of the microphone circuit to the MIC_GND pin of the module as a sense line.
Provide a proper series capacitor at both MIC_P and MIC_N analog uplink inputs for DC blocking (C2 and
C3 100 nF Murata GRM155R71C104K capacitors in Figure 76). This provides a high-pass filter for the
microphone DC bias with proper cut-off frequency according to the value of the resistors of the microphone
supply circuit. Then connect the signal lines to the microphone.
Provide proper parts on each line connected to the external microphone as noise and EMI improvements, to
minimize RF coupling and TDMA noise, according to the custom application requirements.
o Mount an 82 nH series inductor with a Self Resonance Frequency ~1 GHz (e.g. the Murata
LQG15HS82NJ02) on each microphone line (L1 and L2 inductors in Figure 76).
o Mount a 27 pF bypass capacitor (e.g. Murata GRM1555C1H270J) from each microphone line to
solid ground plane (C4 and C5 capacitors in Figure 76).
Use a microphone designed for GSM applications, which typically have internal built-in bypass capacitor.
Provide a 47 nF series capacitor at both SPK_P and SPK_N analog downlink outputs for DC blocking (C8
and C9 Murata GRM155R71C473K capacitors in Figure 76). Then connect the lines to the differential input
of a proper external audio amplifier, differential output which must be connected to the 8 or 4
loudspeaker. (See the Analog Devices SSM2305CPZ filter-less mono 2.8 W class-D Audio Amplifier in the
circuit described in Figure 76.)
Provide proper parts on each line connected to the external loudspeaker as noise and EMI improvements, to
minimize RF coupling, according to EMC requirements of the custom application.
o Mount a 27 pF bypass capacitor (e.g. Murata GRM1555C1H270J) from each loudspeaker line to
solid ground plane (C6 and C7 capacitors in Figure 76).
Provide additional ESD protection (e.g. Bourns CG0402MLE-18G varistor) if the analog audio lines will be
externally accessible on the application device, according to the EMC/ESD requirements of the custom
application. The protection should be mounted close to an accessible point of the line (D1-D4 parts in the
circuit described in Figure 76).