User's Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.6 System function interfaces
- 1.7 Antenna interface
- 1.8 SIM interface
- 1.9 Serial interfaces
- 1.9.1 Asynchronous serial interface (UART)
- 1.9.1.1 UART features
- 1.9.1.2 UART AT interface configuration
- 1.9.1.3 UART signal behavior
- 1.9.1.4 UART and power-saving
- AT+UPSV=0: power saving disabled, fixed active-mode
- AT+UPSV=1: power saving enabled, cyclic idle/active-mode
- AT+UPSV=2: power saving enabled and controlled by the RTS line
- AT+UPSV=3: power saving enabled and controlled by the DTR line
- Wake up via data reception
- Additional considerations for SARA-U2 modules
- 1.9.1.5 Multiplexer protocol (3GPP 27.010)
- 1.9.2 Auxiliary asynchronous serial interface (UART AUX)
- 1.9.3 USB interface
- 1.9.4 DDC (I2C) interface
- 1.9.1 Asynchronous serial interface (UART)
- 1.10 Audio interface
- 1.11 General Purpose Input/Output (GPIO)
- 1.12 Reserved pins (RSVD)
- 1.13 System features
- 1.13.1 Network indication
- 1.13.2 Antenna detection
- 1.13.3 Jamming detection
- 1.13.4 TCP/IP and UDP/IP
- 1.13.5 FTP
- 1.13.6 HTTP
- 1.13.7 SMTP
- 1.13.8 SSL
- 1.13.9 Dual stack IPv4/IPv6
- 1.13.10 Smart temperature management
- 1.13.11 AssistNow clients and GNSS integration
- 1.13.12 Hybrid positioning and CellLocateTM
- 1.13.13 Firmware upgrade Over AT (FOAT)
- 1.13.14 Firmware upgrade Over The Air (FOTA)
- 1.13.15 In-Band modem (eCall / ERA-GLONASS)
- 1.13.16 SIM Access Profile (SAP)
- 1.13.17 Power saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a Low Drop-Out (LDO) linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable Li-Ion or Li-Pol battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for external battery charging circuit
- 2.2.1.8 Guidelines for external battery charging and power path management circuit
- 2.2.1.9 Guidelines for VCC supply layout design
- 2.2.1.10 Guidelines for grounding layout design
- 2.2.2 RTC supply (V_BCKP)
- 2.2.3 Interface supply (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interface
- 2.6 Serial interfaces
- 2.6.1 Asynchronous serial interface (UART)
- 2.6.1.1 Guidelines for UART circuit design
- Providing the full RS-232 functionality (using the complete V.24 link)
- Providing the TXD, RXD, RTS, CTS and DTR lines only (not using the complete V.24 link)
- Providing the TXD, RXD, RTS and CTS lines only (not using the complete V.24 link)
- Providing the TXD and RXD lines only (not using the complete V24 link)
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 Auxiliary asynchronous serial interface (UART AUX)
- 2.6.3 Universal Serial Bus (USB)
- 2.6.4 DDC (I2C) interface
- 2.6.1 Asynchronous serial interface (UART)
- 2.7 Audio interface
- 2.7.1 Analog audio interface
- 2.7.1.1 Guidelines for microphone and speaker connection circuit design (headset / handset modes)
- 2.7.1.2 Guidelines for microphone and loudspeaker connection circuit design (hands-free mode)
- 2.7.1.3 Guidelines for external analog audio device connection circuit design
- 2.7.1.4 Guidelines for analog audio layout design
- 2.7.2 Digital audio interface
- 2.7.1 Analog audio interface
- 2.8 General Purpose Input/Output (GPIO)
- 2.9 Reserved pins (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Thermal guidelines
- 2.13 ESD guidelines
- 2.14 SARA-G350 ATEX integration in explosive atmospheres applications
- 2.15 Schematic for SARA-G3 and SARA-U2 series module integration
- 2.16 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between LISA and SARA-G3 modules
- A.1 Overview
- A.2 Checklist for migration
- A.3 Software migration
- A.4 Hardware migration
- B Migration between SARA-G3 and SARA-U2
- C Glossary
- Related documents
- Revision history
- Contact
SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R08 Objective Specification System description
Page 13 of 188
1.3 Pin-out
Table 4 lists the pin-out of the SARA-G3 and SARA-U2 series modules, with pins grouped by function.
Function
Pin Name
Module
Pin No
I/O
Description
Remarks
Power
VCC
All
51, 52, 53
I
Module supply
input
VCC pins are internally connected each other.
VCC supply circuit affects the RF performance and
compliance of the device integrating the module
with applicable required certification schemes.
See section 1.5.1 for functional description and
requirements for the VCC module supply.
See section 2.2.1 for external circuit design-in.
GND
All
1, 3, 5, 14,
20-22, 30,
32, 43, 50,
54, 55,
57-61,
63-96
N/A
Ground
GND pins are internally connected each other.
External ground connection affects the RF and
thermal performance of the device.
See section 1.5.1 for functional description.
See section 2.2.1 for external circuit design-in.
V_BCKP
All
2
I/O
Real Time Clock
supply
input/output
V_BCKP = 2.3 V (typical) on SARA-G3 series.
V_BCKP = 1.8 V (typical) on SARA-U2 series.
V_BCKP is generated by internal low power linear
regulator when valid VCC supply is present.
See section 1.5.2 for functional description.
See section 2.2.2 for external circuit design-in.
V_INT
All
4
O
Generic Digital
Interfaces supply
output
V_INT = 1.8 V (typical), generated by internal DC/DC
regulator when the module is switched on.
See section 1.5.3 for functional description.
See section 2.2.3 for external circuit design-in.
System
PWR_ON
All
15
I
Power-on input
High input impedance: input voltage level has to be
properly fixed, e.g. adding external pull-up.
See section 1.6.1 for functional description.
See section 2.3.1 for external circuit design-in.
RESET_N
All
18
I
External reset
input
A series Schottky diode is integrated in the module
as protection, and then an internal 10 k pull-up
resistor to V_INT is provided.
See section 1.6.3 for functional description.
See section 2.3.2 for external circuit design-in.
EXT32K
SARA-G300
SARA-G310
31
I
32 kHz input
Input for RTC reference clock, needed to enter the
low power idle-mode and provide RTC functions.
See section 1.6.4 for functional description.
See section 2.3.3 for external circuit design-in.
32K_OUT
SARA-G300
SARA-G310
24
O
32 kHz output
32 kHz output suitable only to feed the EXT32K
input giving the RTC reference clock, allowing low
power idle-mode and RTC functions support.
See section 1.6.5 for functional description.
See section 2.3.3 for external circuit design-in.
Antenna
ANT
All
56
I/O
RF input/output
for antenna
50 nominal characteristic impedance.
Antenna circuit affects the RF performance and
compliance of the device integrating the module
with applicable required certification schemes.
See section 1.7 for functional description and
requirements for the antenna RF interface.
See section 2.4 for external circuit design-in.
ANT_DET
SARA-G340
SARA-G350
SARA-U2
62
I
Input for antenna
detection
ADC input for antenna detection function.
See section 1.7.2 for functional description.
See section 2.4.2 for external circuit design-in.