User's Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.6 System function interfaces
- 1.7 Antenna interface
- 1.8 SIM interface
- 1.9 Serial interfaces
- 1.9.1 Asynchronous serial interface (UART)
- 1.9.1.1 UART features
- 1.9.1.2 UART AT interface configuration
- 1.9.1.3 UART signal behavior
- 1.9.1.4 UART and power-saving
- AT+UPSV=0: power saving disabled, fixed active-mode
- AT+UPSV=1: power saving enabled, cyclic idle/active-mode
- AT+UPSV=2: power saving enabled and controlled by the RTS line
- AT+UPSV=3: power saving enabled and controlled by the DTR line
- Wake up via data reception
- Additional considerations for SARA-U2 modules
- 1.9.1.5 Multiplexer protocol (3GPP 27.010)
- 1.9.2 Auxiliary asynchronous serial interface (UART AUX)
- 1.9.3 USB interface
- 1.9.4 DDC (I2C) interface
- 1.9.1 Asynchronous serial interface (UART)
- 1.10 Audio interface
- 1.11 General Purpose Input/Output (GPIO)
- 1.12 Reserved pins (RSVD)
- 1.13 System features
- 1.13.1 Network indication
- 1.13.2 Antenna detection
- 1.13.3 Jamming detection
- 1.13.4 TCP/IP and UDP/IP
- 1.13.5 FTP
- 1.13.6 HTTP
- 1.13.7 SMTP
- 1.13.8 SSL
- 1.13.9 Dual stack IPv4/IPv6
- 1.13.10 Smart temperature management
- 1.13.11 AssistNow clients and GNSS integration
- 1.13.12 Hybrid positioning and CellLocateTM
- 1.13.13 Firmware upgrade Over AT (FOAT)
- 1.13.14 Firmware upgrade Over The Air (FOTA)
- 1.13.15 In-Band modem (eCall / ERA-GLONASS)
- 1.13.16 SIM Access Profile (SAP)
- 1.13.17 Power saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a Low Drop-Out (LDO) linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable Li-Ion or Li-Pol battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for external battery charging circuit
- 2.2.1.8 Guidelines for external battery charging and power path management circuit
- 2.2.1.9 Guidelines for VCC supply layout design
- 2.2.1.10 Guidelines for grounding layout design
- 2.2.2 RTC supply (V_BCKP)
- 2.2.3 Interface supply (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interface
- 2.6 Serial interfaces
- 2.6.1 Asynchronous serial interface (UART)
- 2.6.1.1 Guidelines for UART circuit design
- Providing the full RS-232 functionality (using the complete V.24 link)
- Providing the TXD, RXD, RTS, CTS and DTR lines only (not using the complete V.24 link)
- Providing the TXD, RXD, RTS and CTS lines only (not using the complete V.24 link)
- Providing the TXD and RXD lines only (not using the complete V24 link)
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 Auxiliary asynchronous serial interface (UART AUX)
- 2.6.3 Universal Serial Bus (USB)
- 2.6.4 DDC (I2C) interface
- 2.6.1 Asynchronous serial interface (UART)
- 2.7 Audio interface
- 2.7.1 Analog audio interface
- 2.7.1.1 Guidelines for microphone and speaker connection circuit design (headset / handset modes)
- 2.7.1.2 Guidelines for microphone and loudspeaker connection circuit design (hands-free mode)
- 2.7.1.3 Guidelines for external analog audio device connection circuit design
- 2.7.1.4 Guidelines for analog audio layout design
- 2.7.2 Digital audio interface
- 2.7.1 Analog audio interface
- 2.8 General Purpose Input/Output (GPIO)
- 2.9 Reserved pins (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Thermal guidelines
- 2.13 ESD guidelines
- 2.14 SARA-G350 ATEX integration in explosive atmospheres applications
- 2.15 Schematic for SARA-G3 and SARA-U2 series module integration
- 2.16 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between LISA and SARA-G3 modules
- A.1 Overview
- A.2 Checklist for migration
- A.3 Software migration
- A.4 Hardware migration
- B Migration between SARA-G3 and SARA-U2
- C Glossary
- Related documents
- Revision history
- Contact
SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R08 Objective Specification Design-in
Page 127 of 188
Figure 74 shows an application circuit example for connecting a SARA-U2 cellular module to a u-blox 3.0 V
GNSS receiver:
As the SDA and SCL pins of the SARA-U2 cellular module are not tolerant up to 3.0 V, the connection to
the related I
2
C pins of the u-blox 3.0 V GNSS receiver must be provided using a proper I
2
C-bus Bidirectional
Voltage Translator (e.g. TI TCA9406, which additionally provides the partial power down feature so that the
GNSS 3.0 V supply can be ramped up before the V_INT 1.8 V cellular supply), with proper pull-up resistors.
The GPIO2 is connected to the active-high enable pin of the voltage regulator that supplies the u-blox 3.0 V
GNSS receiver providing the “GNSS supply enable” function. A pull-down resistor is provided to avoid a
switch on of the positioning receiver when the cellular module is switched off or in the reset state.
As the GPIO3 and GPIO4 pins of the SARA-U2 cellular modules are not tolerant up to 3.0 V, the connection
to the related pins of the u-blox 3.0 V GNSS receiver must be provided using a proper Unidirectional General
Purpose Voltage Translator (e.g. TI SN74AVC2T245, which additionally provides the partial power down
feature so that the 3.0 V GNSS supply can be also ramped up before the V_INT 1.8 V cellular supply).
The V_BCKP supply output of the cellular module can be directly connected to the V_BCKP backup supply
input pin of the GNSS receiver as in the application circuit for a u-blox 1.8 V GNSS receiver.
SARA-U2 series
u-blox GNSS
3.0 V receiver
24
GPIO3
25
GPIO4
1V8
B1 A1
GND
U3
B2A2
VCCBVCCA
Unidirectional
Voltage Translator
C4
C5
3V0
TxD1
EXTINT0
R1
INOUT
GND
GNSS LDO
Regulator
SHDN
R2
VMAIN3V0
U1
23
GPIO2
26
SDA
27
SCL
R4 R5
1V8
SDA_A SDA_B
GND
U2
SCL_ASCL_B
VCCA
VCCB
I2C-bus Bidirectional
Voltage Translator
4
V_INT
C1
C2
C3
R3
SDA2
SCL2
VCC
DIR1
DIR2
2
V_BCKPV_BCKP
OE
OE
GNSS data ready
GNSS RTC sharing
GNSS supply enabled
Figure 74: Application circuit for connecting SARA-U2 modules to u-blox 3.0 V GNSS receivers
Reference
Description
Part Number - Manufacturer
R1, R2, R4, R5
4.7 kΩ Resistor 0402 5% 0.1 W
RC0402JR-074K7L - Yageo Phycomp
R3
47 kΩ Resistor 0402 5% 0.1 W
RC0402JR-0747KL - Yageo Phycomp
C2, C3, C4, C5
100 nF Capacitor Ceramic X5R 0402 10% 10V
GRM155R71C104KA01 - Murata
U1, C1
Voltage Regulator for GNSS receiver and related
output bypass capacitor
See GNSS receiver Hardware Integration Manual
U2
I2C-bus Bidirectional Voltage Translator
TCA9406DCUR - Texas Instruments
U3
Generic Unidirectional Voltage Translator
SN74AVC2T245 - Texas Instruments
Table 40: Components for connecting SARA-U2 modules to u-blox 3.0 V GNSS receivers