User's Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.6 System function interfaces
- 1.7 Antenna interface
- 1.8 SIM interface
- 1.9 Serial interfaces
- 1.9.1 Asynchronous serial interface (UART)
- 1.9.1.1 UART features
- 1.9.1.2 UART AT interface configuration
- 1.9.1.3 UART signal behavior
- 1.9.1.4 UART and power-saving
- AT+UPSV=0: power saving disabled, fixed active-mode
- AT+UPSV=1: power saving enabled, cyclic idle/active-mode
- AT+UPSV=2: power saving enabled and controlled by the RTS line
- AT+UPSV=3: power saving enabled and controlled by the DTR line
- Wake up via data reception
- Additional considerations for SARA-U2 modules
- 1.9.1.5 Multiplexer protocol (3GPP 27.010)
- 1.9.2 Auxiliary asynchronous serial interface (UART AUX)
- 1.9.3 USB interface
- 1.9.4 DDC (I2C) interface
- 1.9.1 Asynchronous serial interface (UART)
- 1.10 Audio interface
- 1.11 General Purpose Input/Output (GPIO)
- 1.12 Reserved pins (RSVD)
- 1.13 System features
- 1.13.1 Network indication
- 1.13.2 Antenna detection
- 1.13.3 Jamming detection
- 1.13.4 TCP/IP and UDP/IP
- 1.13.5 FTP
- 1.13.6 HTTP
- 1.13.7 SMTP
- 1.13.8 SSL
- 1.13.9 Dual stack IPv4/IPv6
- 1.13.10 Smart temperature management
- 1.13.11 AssistNow clients and GNSS integration
- 1.13.12 Hybrid positioning and CellLocateTM
- 1.13.13 Firmware upgrade Over AT (FOAT)
- 1.13.14 Firmware upgrade Over The Air (FOTA)
- 1.13.15 In-Band modem (eCall / ERA-GLONASS)
- 1.13.16 SIM Access Profile (SAP)
- 1.13.17 Power saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a Low Drop-Out (LDO) linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable Li-Ion or Li-Pol battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for external battery charging circuit
- 2.2.1.8 Guidelines for external battery charging and power path management circuit
- 2.2.1.9 Guidelines for VCC supply layout design
- 2.2.1.10 Guidelines for grounding layout design
- 2.2.2 RTC supply (V_BCKP)
- 2.2.3 Interface supply (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interface
- 2.6 Serial interfaces
- 2.6.1 Asynchronous serial interface (UART)
- 2.6.1.1 Guidelines for UART circuit design
- Providing the full RS-232 functionality (using the complete V.24 link)
- Providing the TXD, RXD, RTS, CTS and DTR lines only (not using the complete V.24 link)
- Providing the TXD, RXD, RTS and CTS lines only (not using the complete V.24 link)
- Providing the TXD and RXD lines only (not using the complete V24 link)
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 Auxiliary asynchronous serial interface (UART AUX)
- 2.6.3 Universal Serial Bus (USB)
- 2.6.4 DDC (I2C) interface
- 2.6.1 Asynchronous serial interface (UART)
- 2.7 Audio interface
- 2.7.1 Analog audio interface
- 2.7.1.1 Guidelines for microphone and speaker connection circuit design (headset / handset modes)
- 2.7.1.2 Guidelines for microphone and loudspeaker connection circuit design (hands-free mode)
- 2.7.1.3 Guidelines for external analog audio device connection circuit design
- 2.7.1.4 Guidelines for analog audio layout design
- 2.7.2 Digital audio interface
- 2.7.1 Analog audio interface
- 2.8 General Purpose Input/Output (GPIO)
- 2.9 Reserved pins (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Thermal guidelines
- 2.13 ESD guidelines
- 2.14 SARA-G350 ATEX integration in explosive atmospheres applications
- 2.15 Schematic for SARA-G3 and SARA-U2 series module integration
- 2.16 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between LISA and SARA-G3 modules
- A.1 Overview
- A.2 Checklist for migration
- A.3 Software migration
- A.4 Hardware migration
- B Migration between SARA-G3 and SARA-U2
- C Glossary
- Related documents
- Revision history
- Contact
SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R08 Objective Specification Design-in
Page 113 of 188
Limit capacitance and series resistance on each SIM signal (SIM_CLK, SIM_IO, SIM_RST) to match the
requirements for the SIM interface (27.7 ns is the maximum allowed rise time on the SIM_CLK line, 1.0 µs is
the maximum allowed rise time on the SIM_IO and SIM_RST lines)
SARA-G3 / SARA-U2
C1
FIRST
SIM CARD
VPP (C6)
VCC (C1)
IO (C7)
CLK (C3)
RST (C2)
GND (C5)
C2 C3 C5
J1
C4
D1 D2 D3 D4
GND
U1
41
VSIM
VSIM
1VSIM
2VSIM
VCC
C11
4PDT
Analog
Switch
3V8
39
SIM_IO
DAT
1DAT
2DAT
38
SIM_CLK
CLK
1CLK
2CLK
40
SIM_RST
RST
1RST
2RST
SEL
SECOND
SIM CARD
VPP (C6)
VCC (C1)
IO (C7)
CLK (C3)
RST (C2)
GND (C5)
J2
C6 C7 C8 C10
C9
D5 D6 D7 D8
Application
Processor
GPIO
R1
Figure 57: Application circuit for the connection to two removable SIM cards, with SIM detection implemented
Reference
Description
Part Number - Manufacturer
C1 – C4, C6 – C9
33 pF Capacitor Ceramic C0G 0402 5% 25 V
GRM1555C1H330JZ01 - Murata
C5, C10, C11
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C104KA01 - Murata
D1 – D8
Very Low Capacitance ESD Protection
PESD0402-140 - Tyco Electronics
R1
47 kΩ Resistor 0402 5% 0.1 W
RC0402JR-0747KL- Yageo Phycomp
J1, J2
SIM Card Holder
6 positions, without card presence switch
Various Manufacturers,
C707 10M006 136 2 - Amphenol
U1
4PDT Analog Switch,
with Low On-Capacitance and Low On-Resistance
FSA2567 - Fairchild Semiconductor
Table 30: Example of components for the connection to two removable SIM cards, with SIM detection implemented
2.5.1.2 Guidelines for SIM layout design
The layout of the SIM card interface lines (VSIM, SIM_CLK, SIM_IO, SIM_RST) may be critical if the SIM card is
placed far away from the SARA-G3 and SARA-U2 series modules or in close proximity to the RF antenna: these
two cases should be avoided or at least mitigated as described below.
In the first case, the long connection can cause the radiation of some harmonics of the digital data frequency as
any other digital interface: keep the traces short and avoid coupling with RF line or sensitive analog inputs.
In the second case, the same harmonics can be picked up and create self-interference that can reduce the
sensitivity of GSM / UMTS receiver channels whose carrier frequency is coincidental with harmonic frequencies:
placing the RF bypass capacitors suggested in Figure 56 near the SIM connector will mitigate the problem.
In addition, since the SIM card is typically accessed by the end user, it can be subjected to ESD discharges: add
adequate ESD protection as suggested in Figure 56 to protect module SIM pins near the SIM connector.
Limit capacitance and series resistance on each SIM signal to match the SIM specifications: the connections
should always be kept as short as possible.
Avoid coupling with any sensitive analog circuit, since the SIM signals can cause the radiation of some harmonics
of the digital data frequency