User's Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.6 System function interfaces
- 1.7 Antenna interface
- 1.8 SIM interface
- 1.9 Serial interfaces
- 1.9.1 Asynchronous serial interface (UART)
- 1.9.1.1 UART features
- 1.9.1.2 UART AT interface configuration
- 1.9.1.3 UART signal behavior
- 1.9.1.4 UART and power-saving
- AT+UPSV=0: power saving disabled, fixed active-mode
- AT+UPSV=1: power saving enabled, cyclic idle/active-mode
- AT+UPSV=2: power saving enabled and controlled by the RTS line
- AT+UPSV=3: power saving enabled and controlled by the DTR line
- Wake up via data reception
- Additional considerations for SARA-U2 modules
- 1.9.1.5 Multiplexer protocol (3GPP 27.010)
- 1.9.2 Auxiliary asynchronous serial interface (UART AUX)
- 1.9.3 USB interface
- 1.9.4 DDC (I2C) interface
- 1.9.1 Asynchronous serial interface (UART)
- 1.10 Audio interface
- 1.11 General Purpose Input/Output (GPIO)
- 1.12 Reserved pins (RSVD)
- 1.13 System features
- 1.13.1 Network indication
- 1.13.2 Antenna detection
- 1.13.3 Jamming detection
- 1.13.4 TCP/IP and UDP/IP
- 1.13.5 FTP
- 1.13.6 HTTP
- 1.13.7 SMTP
- 1.13.8 SSL
- 1.13.9 Dual stack IPv4/IPv6
- 1.13.10 Smart temperature management
- 1.13.11 AssistNow clients and GNSS integration
- 1.13.12 Hybrid positioning and CellLocateTM
- 1.13.13 Firmware upgrade Over AT (FOAT)
- 1.13.14 Firmware upgrade Over The Air (FOTA)
- 1.13.15 In-Band modem (eCall / ERA-GLONASS)
- 1.13.16 SIM Access Profile (SAP)
- 1.13.17 Power saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a Low Drop-Out (LDO) linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable Li-Ion or Li-Pol battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for external battery charging circuit
- 2.2.1.8 Guidelines for external battery charging and power path management circuit
- 2.2.1.9 Guidelines for VCC supply layout design
- 2.2.1.10 Guidelines for grounding layout design
- 2.2.2 RTC supply (V_BCKP)
- 2.2.3 Interface supply (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interface
- 2.6 Serial interfaces
- 2.6.1 Asynchronous serial interface (UART)
- 2.6.1.1 Guidelines for UART circuit design
- Providing the full RS-232 functionality (using the complete V.24 link)
- Providing the TXD, RXD, RTS, CTS and DTR lines only (not using the complete V.24 link)
- Providing the TXD, RXD, RTS and CTS lines only (not using the complete V.24 link)
- Providing the TXD and RXD lines only (not using the complete V24 link)
- Additional considerations
- 2.6.1.2 Guidelines for UART layout design
- 2.6.1.1 Guidelines for UART circuit design
- 2.6.2 Auxiliary asynchronous serial interface (UART AUX)
- 2.6.3 Universal Serial Bus (USB)
- 2.6.4 DDC (I2C) interface
- 2.6.1 Asynchronous serial interface (UART)
- 2.7 Audio interface
- 2.7.1 Analog audio interface
- 2.7.1.1 Guidelines for microphone and speaker connection circuit design (headset / handset modes)
- 2.7.1.2 Guidelines for microphone and loudspeaker connection circuit design (hands-free mode)
- 2.7.1.3 Guidelines for external analog audio device connection circuit design
- 2.7.1.4 Guidelines for analog audio layout design
- 2.7.2 Digital audio interface
- 2.7.1 Analog audio interface
- 2.8 General Purpose Input/Output (GPIO)
- 2.9 Reserved pins (RSVD)
- 2.10 Module placement
- 2.11 Module footprint and paste mask
- 2.12 Thermal guidelines
- 2.13 ESD guidelines
- 2.14 SARA-G350 ATEX integration in explosive atmospheres applications
- 2.15 Schematic for SARA-G3 and SARA-U2 series module integration
- 2.16 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- Appendix
- A Migration between LISA and SARA-G3 modules
- A.1 Overview
- A.2 Checklist for migration
- A.3 Software migration
- A.4 Hardware migration
- B Migration between SARA-G3 and SARA-U2
- C Glossary
- Related documents
- Revision history
- Contact
SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R08 Objective Specification Design-in
Page 112 of 188
Guidelines for dual SIM card / chip connection
Two SIM card / chip can be connected to the SIM interface of SARA-G3 and SARA-U2 modules as described in
the application circuit of Figure 57.
SARA-G3 and SARA-U2 modules do not support the usage of two SIM at the same time, but two SIM can be
populated on the application board providing a proper switch to connect only the first SIM or only the second
SIM per time to the SIM interface of the SARA-G3 and SARA-U2 modules as described in Figure 57.
SARA-G3 modules do not support SIM hot insertion / removal: the module is able to properly use a SIM only if
the SIM / module physical connection is provided before the module boot and then held for normal operation.
Switching from one SIM to another one can only be properly done within one of these two time periods:
after module switch-off by the AT+CPWROFF and before module switch-on by PWR_ON
after network deregistration by AT+COPS=2 and before module reset by AT+CFUN=16 or RESET_N
SARA-U2 modules support SIM hot insertion / removal on the SIM_DET pin: if the feature is enabled using the
specific AT commands (refer to sections 1.8.2 and 1.11, and to the u-blox AT Commands Manual [3], +UGPIOC,
+UDCONF commands), the switch from first SIM to the second SIM can be properly done when a Low logic level
is present on the SIM_DET pin (‘SIM not inserted’ = SIM interface not enabled), without the necessity of a
module re-boot, so that the SIM interface will be re-enabled by the module to use the second SIM when an High
logic level will be re-applied on the SIM_DET pin.
In the application circuit example represented in Figure 57, the application processor will drive the SIM switch
using its own GPIO to properly select the SIM that is used by the module. Another GPIO may be used to handle
the SIM hot insertion / removal function of SARA-U2 modules, which can also be handled by other external
circuits or by the cellular module GPIO according to the application requirements.
The dual SIM connection circuit described in Figure 57 can be implemented for SIM chips as well, providing
proper connection between SIM switch and SIM chip as described in Figure 55.
If it is required to switch between more than two SIM, a circuit similar to the one described in Figure 57 can be
implemented: for example, in case of four SIM circuit, using proper four-pole four-throw switch (or for example
four single-pole four-throw switches) instead of the suggested four-pole double-throw switch.
Follow these guidelines connecting the module to two SIM connectors:
Connect the contacts C1 (VCC) and C6 (VPP) of the two UICC / SIM to the VSIM pin of the module by
means of a proper low on resistance (i.e. few ohms) and low on capacitance (i.e. few pF) double-throw
analog switch (e.g. Fairchild FSA2567) to ensure high-speed data transfer according to SIM requirements
Connect the contact C7 (I/O) of the two UICC / SIM to the SIM_IO pin of the module by means of a proper
low on resistance (i.e. few ohms) and low on capacitance (i.e. few pF) double-throw analog switch (e.g.
Fairchild FSA2567) to ensure high-speed data transfer according to SIM requirements
Connect the contact C3 (CLK) of the two UICC / SIM to the SIM_CLK pin of the module by means of a
proper low on resistance (i.e. few ohms) and low on capacitance (i.e. few pF) double-throw analog switch
(e.g. Fairchild FSA2567) to ensure high-speed data transfer according to SIM requirements
Connect the contact C2 (RST) of the two UICC / SIM to the SIM_RST pin of the module by means of a
proper low on resistance (i.e. few ohms) and low on capacitance (i.e. few pF) double-throw analog switch
(e.g. Fairchild FSA2567) to ensure high-speed data transfer according to SIM requirements
Connect the contact C5 (GND) of the two UICC / SIM to ground
Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) at the SIM supply line (VSIM), close to
the related pad of the two SIM connectors, to prevent digital noise
Provide a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) on each SIM line
(VSIM, SIM_CLK, SIM_IO, SIM_RST), very close to each related pad of the two SIM connectors, to prevent
RF coupling especially in case the RF antenna is placed closer than 10 - 30 cm from the SIM card holders
Provide a very low capacitance (i.e. less than 10 pF) ESD protection (e.g. Tyco Electronics PESD0402-140) on
each externally accessible SIM line, close to each related pad of the two SIM connectors, according to the
EMC/ESD requirements of the custom application