Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Applications
- 1.3 Architecture
- 1.4 Pin assignments
- 1.5 Supply interfaces
- 1.6 System function interfaces
- 1.7 Debug
- 1.8 GPIO pins
- 1.9 Analog interfaces
- 1.10 Serial interfaces
- 1.10.1 Universal Asynchronous Receiver/Transmitter (UART)
- 1.10.2 Serial Peripheral Interface (SPI)
- 1.10.3 Quad Serial Peripheral Interface (QSPI)
- 1.10.4 Inter-Integrated Circuit (I2C) interface
- 1.10.5 Pulse Width Modulation (PWM) interface
- 1.10.6 Inter-IC Sound (I2S) interface
- 1.10.7 Pulse Density Modulation (PDM) interface
- 1.10.8 USB 2.0 device interface
- 1.11 Antenna interface
- 1.12 Reserved pins (RSVD)
- 1.13 GND pins
- 2 Software
- 3 Flashing application software
- 4 Design-in
- 5 Handling and soldering
- 6 Regulatory information and requirements
- 6.1 ETSI – European market
- 6.2 FCC/ISED – US/Canadian markets
- 6.3 MIC - Japanese market (pending)
- 6.4 NCC – Taiwanese market (pending)
- 6.5 KCC – South Korean market (pending)
- 6.6 ANATEL Brazil compliance (pending)
- 6.7 Australia and New Zealand regulatory compliance (pending)
- 6.8 South Africa regulatory compliance (pending)
- 6.9 Integration checklist
- 6.10 Pre-approved antennas list
- 7 Technology standards compliance
- 8 Product testing
- Appendix
- A Glossary
- B Antenna reference designs
- Related documents
- Revision history
- Contact
NORA-B1 series - System integration manual
UBX-20027617 - R04 System description Page 8 of 61
C1-Public
1.3 Architecture
1.3.1 Block diagram
Figure 1: NORA-B1 series block diagram
1.3.2 Hardware options
NORA-B1 series modules use an identical hardware configuration except for the different antenna
solutions. An external 32.768 kHz low-frequency crystal can be used if LFCLK accuracy better than
+/-250 ppm is required. DC-DC converters are integrated to provide higher efficiency across
operating modes.
1.3.3 Software options
NORA-B1 series modules are open CPU solutions that allow custom applications to be developed
with the Nordic Semiconductor nRF Connect SDK, which includes the Zephyr Real Time Operating
System (RTOS), MCUboot bootloader, and nrfxdrv drivers for optimizing connected peripheral
performance.
1.4 Pin assignments
For information about the function, configuration, and characteristics of module pins, see the
NORA-B1 series data sheet [1].
1.5 Supply interfaces
1.5.1 Main supply input
NORA-B1 utilizes three power inputs, VDDH, VDD, and VBUS. These inputs connect to internal
regulators that provide the application and network core operating voltages, USB subsystem power,
and GPIO voltage references.
In normal voltage mode, a single power source is connected to both VDDH and VDD. This bypasses
the high voltage regulator (VREGH). The GPIO voltage is equal to the external power source voltage.