Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Applications
- 1.3 Architecture
- 1.4 Pin assignments
- 1.5 Supply interfaces
- 1.6 System function interfaces
- 1.7 Debug
- 1.8 GPIO pins
- 1.9 Analog interfaces
- 1.10 Serial interfaces
- 1.10.1 Universal Asynchronous Receiver/Transmitter (UART)
- 1.10.2 Serial Peripheral Interface (SPI)
- 1.10.3 Quad Serial Peripheral Interface (QSPI)
- 1.10.4 Inter-Integrated Circuit (I2C) interface
- 1.10.5 Pulse Width Modulation (PWM) interface
- 1.10.6 Inter-IC Sound (I2S) interface
- 1.10.7 Pulse Density Modulation (PDM) interface
- 1.10.8 USB 2.0 device interface
- 1.11 Antenna interface
- 1.12 Reserved pins (RSVD)
- 1.13 GND pins
- 2 Software
- 3 Flashing application software
- 4 Design-in
- 5 Handling and soldering
- 6 Regulatory information and requirements
- 6.1 ETSI – European market
- 6.2 FCC/ISED – US/Canadian markets
- 6.3 MIC - Japanese market (pending)
- 6.4 NCC – Taiwanese market (pending)
- 6.5 KCC – South Korean market (pending)
- 6.6 ANATEL Brazil compliance (pending)
- 6.7 Australia and New Zealand regulatory compliance (pending)
- 6.8 South Africa regulatory compliance (pending)
- 6.9 Integration checklist
- 6.10 Pre-approved antennas list
- 7 Technology standards compliance
- 8 Product testing
- Appendix
- A Glossary
- B Antenna reference designs
- Related documents
- Revision history
- Contact
NORA-B1 series - System integration manual
UBX-20027617 - R04 Design-in Page 34 of 61
C1-Public
NORA-B1 module and the remote NFC transmitter is always within three meters during
transmission.
Figure 11: NFC antenna design
4.7.1.1 Battery protection
If the NFC antenna is exposed to a strong NFC field, current may flow in the opposite direction on
the supply because of parasitic diodes and ESD structures.
If the battery used does not tolerate a return current, protection must be placed between the
battery and the device to protect the battery. A series Schottky diode, or an “ideal diode” chip may
be used, such as the Maxim MAX40203AUK+T.
4.8 General high-speed layout guidelines
These general design guidelines are considered as best practices and are valid for any bus present in
NORA-B1 series modules; designers should prioritize the layout of higher speed buses. Low
frequency signals are generally not critical for layout.
⚠ One exception is represented by high impedance traces (such as signals driven by weak pull
resistors) that may be affected by crosstalk. For those traces, a supplementary isolation of 4w
(four times the line width) from other buses is recommended.
4.8.1 General considerations for schematic design and PCB floor-planning
• Verify which signal bus requires termination and add series resistor terminations to the
schematics.
• Carefully consider the placement of the module with respect to antenna position and host
processor.
• Verify with PCB manufacturer allowable stack-ups and controlled impedance dimensioning.
• Verify that the power supply design and power sequence are compliant with NORA-B1 series
module specification described in the NORA-B1 data sheet [1].