Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Applications
- 1.3 Architecture
- 1.4 Pin assignments
- 1.5 Supply interfaces
- 1.6 System function interfaces
- 1.7 Debug
- 1.8 GPIO pins
- 1.9 Analog interfaces
- 1.10 Serial interfaces
- 1.10.1 Universal Asynchronous Receiver/Transmitter (UART)
- 1.10.2 Serial Peripheral Interface (SPI)
- 1.10.3 Quad Serial Peripheral Interface (QSPI)
- 1.10.4 Inter-Integrated Circuit (I2C) interface
- 1.10.5 Pulse Width Modulation (PWM) interface
- 1.10.6 Inter-IC Sound (I2S) interface
- 1.10.7 Pulse Density Modulation (PDM) interface
- 1.10.8 USB 2.0 device interface
- 1.11 Antenna interface
- 1.12 Reserved pins (RSVD)
- 1.13 GND pins
- 2 Software
- 3 Flashing application software
- 4 Design-in
- 5 Handling and soldering
- 6 Regulatory information and requirements
- 6.1 ETSI – European market
- 6.2 FCC/ISED – US/Canadian markets
- 6.3 MIC - Japanese market (pending)
- 6.4 NCC – Taiwanese market (pending)
- 6.5 KCC – South Korean market (pending)
- 6.6 ANATEL Brazil compliance (pending)
- 6.7 Australia and New Zealand regulatory compliance (pending)
- 6.8 South Africa regulatory compliance (pending)
- 6.9 Integration checklist
- 6.10 Pre-approved antennas list
- 7 Technology standards compliance
- 8 Product testing
- Appendix
- A Glossary
- B Antenna reference designs
- Related documents
- Revision history
- Contact
NORA-B1 series - System integration manual
UBX-20027617 - R04 Design-in Page 32 of 61
C1-Public
such as spring-loaded connectors (e.g., Tag-Connect-pads [7]) or simple test points can be used as
well.
Keep in mind that a minimum of four signals are required for the SWD interface to work: SWDIO,
SWDCLK, GND and VDD reference are needed for the SWD interface to work. nRESET and SWO are
optional, though suggested. Pin 9 connected to GND is only needed when used with an EVK
providing an on-board debugger, such as the EVK-NORA-B1.
Figure 9: Cortex-M debug connector pin out on EVK-NORA-B1 for SWD
4.6 Serial interfaces
4.6.1 UART
The layout of the UART bus should be made so that noise injection and cross talk are avoided.
Use hardware flow control with RTS/CTS to prevent temporary UART buffer overrun.
RTS/CTS flow control signals are active low. The UART can transmit when either of these signals are
set to “0” (ON state = low level).
• CTS is an input to NORA-B1. The module can transmit when the host sets this signal to “0” (ON
state = low level).
• RTS is an output from NORA-B1. The module sets this signal to “0” (ON state = low level) when it
is ready to receive transmission.
4.6.2 USB
The layout of the USB bus should be made so that noise injection and crosstalk are avoided.
The signals MODUSB_DP and MODUSB_DM have controlled 90 Ω differential-pair impedance.
Power and ground connections from the upstream USB host should be filtered and ESD protected.
nRESET = 10
N/C = 8
SWO = 6
SWCLK = 4
SWDIO = 2
9 = GND
7 = N/C (may be keyed)
5 = GND
3 = GND
1 = VDD reference input