Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Applications
- 1.3 Architecture
- 1.4 Pin assignments
- 1.5 Supply interfaces
- 1.6 System function interfaces
- 1.7 Debug
- 1.8 GPIO pins
- 1.9 Analog interfaces
- 1.10 Serial interfaces
- 1.10.1 Universal Asynchronous Receiver/Transmitter (UART)
- 1.10.2 Serial Peripheral Interface (SPI)
- 1.10.3 Quad Serial Peripheral Interface (QSPI)
- 1.10.4 Inter-Integrated Circuit (I2C) interface
- 1.10.5 Pulse Width Modulation (PWM) interface
- 1.10.6 Inter-IC Sound (I2S) interface
- 1.10.7 Pulse Density Modulation (PDM) interface
- 1.10.8 USB 2.0 device interface
- 1.11 Antenna interface
- 1.12 Reserved pins (RSVD)
- 1.13 GND pins
- 2 Software
- 3 Flashing application software
- 4 Design-in
- 5 Handling and soldering
- 6 Regulatory information and requirements
- 6.1 ETSI – European market
- 6.2 FCC/ISED – US/Canadian markets
- 6.3 MIC - Japanese market (pending)
- 6.4 NCC – Taiwanese market (pending)
- 6.5 KCC – South Korean market (pending)
- 6.6 ANATEL Brazil compliance (pending)
- 6.7 Australia and New Zealand regulatory compliance (pending)
- 6.8 South Africa regulatory compliance (pending)
- 6.9 Integration checklist
- 6.10 Pre-approved antennas list
- 7 Technology standards compliance
- 8 Product testing
- Appendix
- A Glossary
- B Antenna reference designs
- Related documents
- Revision history
- Contact
NORA-B1 series - System integration manual
UBX-20027617 - R04 Design-in Page 31 of 61
C1-Public
Figure 8: Size of the RF keep-out area for the NORA-B106 module
4.4 Supply interfaces
4.4.1 Module supply design
A good connection of the module’s VDD and/or VDDH pins with DC supply source is required for
proper module operation. The guidelines are summarized below:
• The VDD and VDDH connections must be sufficient to support the maximum current of the
application.
• The VDD and VDDH connections must be routed through a PCB area separated from sensitive
analog signals and sensitive functional units. It is a good practice to interpose at least one layer
of PCB ground between the VDD track and other signal routing.
There is no strict requirement for adding bypass capacitance to the supply net close to the module.
But depending on the layout of the supply net and other consumers on the same net, r capacitors
might still be beneficial. Though the GND pins are internally connected, connect all the available pins
to solid ground on the application board, as a good (low impedance) connection to an external
ground can minimize power loss and improve RF and thermal performance.
4.5 Debug interface
NORA-B1 modules support Serial Wire Debug (SWD) and Serial Wire Viewer. When designing a host
board with the NORA-B1, the SWD interface must be made available. The module does not contain
any software from the factory and to initially flash the module the SWD interface must be used.
During software development, a debug connector to the module is useful.
Figure 9 shows the pinout of the 10-pin, 50 mil pitch connector that is used on the EVK-NORA-B1.
This is a compact debug header that can be used on a host board design as well. Other solutions
RF keep
-out edge shall extend across the entire host PCB