Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Applications
- 1.3 Architecture
- 1.4 Pin assignments
- 1.5 Supply interfaces
- 1.6 System function interfaces
- 1.7 Debug
- 1.8 GPIO pins
- 1.9 Analog interfaces
- 1.10 Serial interfaces
- 1.10.1 Universal Asynchronous Receiver/Transmitter (UART)
- 1.10.2 Serial Peripheral Interface (SPI)
- 1.10.3 Quad Serial Peripheral Interface (QSPI)
- 1.10.4 Inter-Integrated Circuit (I2C) interface
- 1.10.5 Pulse Width Modulation (PWM) interface
- 1.10.6 Inter-IC Sound (I2S) interface
- 1.10.7 Pulse Density Modulation (PDM) interface
- 1.10.8 USB 2.0 device interface
- 1.11 Antenna interface
- 1.12 Reserved pins (RSVD)
- 1.13 GND pins
- 2 Software
- 3 Flashing application software
- 4 Design-in
- 5 Handling and soldering
- 6 Regulatory information and requirements
- 6.1 ETSI – European market
- 6.2 FCC/ISED – US/Canadian markets
- 6.3 MIC - Japanese market (pending)
- 6.4 NCC – Taiwanese market (pending)
- 6.5 KCC – South Korean market (pending)
- 6.6 ANATEL Brazil compliance (pending)
- 6.7 Australia and New Zealand regulatory compliance (pending)
- 6.8 South Africa regulatory compliance (pending)
- 6.9 Integration checklist
- 6.10 Pre-approved antennas list
- 7 Technology standards compliance
- 8 Product testing
- Appendix
- A Glossary
- B Antenna reference designs
- Related documents
- Revision history
- Contact
NORA-B1 series - System integration manual
UBX-20027617 - R04 Flashing application software Page 22 of 61
C1-Public
3 Flashing application software
Both the application and network cores of the NORA-B1 modules are flashed over a common SWD
interface. See also [20].
3.1 SWD interface
A SEGGER J-Link programmer is required to program the NORA-B1 module flash over the SWD port.
☞ The EVK-NORA-B10x evaluation kit includes a J-LINK-OB that is used to program and debug
the on-board NORA-B1 as well as the target hardware for ANNA-B1, BMD-3, NINA-B1,
NINA-B3, NINA-B4, and NORA-B1 modules.
3.2 Readback protection
By default, readback protection is enabled in NORA-B1. To use the SWD interface, the
UICR.APPROTECT register must be set to “unprotected”. In addition, the code running on the core
must set the CTRL-AP.APPROTECT.DISABLE register to the same value. Each core is separately
protected. The application core also contains UICR.SECUREAPPROTECT and CTRL-
AP.SECUREAPPROTECT.DISABLE registers which may be enabled separately to block all secure access
through the application core. See also [16].
☞ NORA-B1 is provided from the factory with readback protection fully disabled.
⚠ Open CPU application firmware and the UICR must include these settings to debug or reprogram
NORA-B1. If these settings are not provided, each core needs to be recovered to enable the SWD
port.
3.3 Recovery
If SWD access becomes disabled, NORA-B1 must be recovered. west can perform a full recovery of
both cores with a single command:
c:\ubx>we– --recover
If nrfjprog is used, each core of NORA-B1 must be recovered separately. This process fully erases
both the flash and UICR:
c:\ubx>nrfjprog -f nrf– --coprocessor CP_NETWO– --recover
Recovering device. This operation might take 30s.
Writing image to disable ap protect.
Erasing user code and UICR flash areas.
c:\ubx>nrfjprog -f nrf– --recover
Recovering device. This operation might take 30s.
Writing image to disable ap protect.
Erasing user code and UICR flash areas.
⚠ When the network core is recovered, it erases both the network and application cores. When the
application core is recovered, only the application core is affected. For this reason, it is important
to first recover the network core so the readback protection can be properly disabled.
☞ The Bluetooth device address is erased this process. For information about restoring the
address to the UICR, see also Bluetooth device (MAC) address and other production data.
3.4 Programming
SES can be used to interactively erase, program, and debug application core and network core code.