Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Applications
- 1.3 Architecture
- 1.4 Pin assignments
- 1.5 Supply interfaces
- 1.6 System function interfaces
- 1.7 Debug
- 1.8 GPIO pins
- 1.9 Analog interfaces
- 1.10 Serial interfaces
- 1.10.1 Universal Asynchronous Receiver/Transmitter (UART)
- 1.10.2 Serial Peripheral Interface (SPI)
- 1.10.3 Quad Serial Peripheral Interface (QSPI)
- 1.10.4 Inter-Integrated Circuit (I2C) interface
- 1.10.5 Pulse Width Modulation (PWM) interface
- 1.10.6 Inter-IC Sound (I2S) interface
- 1.10.7 Pulse Density Modulation (PDM) interface
- 1.10.8 USB 2.0 device interface
- 1.11 Antenna interface
- 1.12 Reserved pins (RSVD)
- 1.13 GND pins
- 2 Software
- 3 Flashing application software
- 4 Design-in
- 5 Handling and soldering
- 6 Regulatory information and requirements
- 6.1 ETSI – European market
- 6.2 FCC/ISED – US/Canadian markets
- 6.3 MIC - Japanese market (pending)
- 6.4 NCC – Taiwanese market (pending)
- 6.5 KCC – South Korean market (pending)
- 6.6 ANATEL Brazil compliance (pending)
- 6.7 Australia and New Zealand regulatory compliance (pending)
- 6.8 South Africa regulatory compliance (pending)
- 6.9 Integration checklist
- 6.10 Pre-approved antennas list
- 7 Technology standards compliance
- 8 Product testing
- Appendix
- A Glossary
- B Antenna reference designs
- Related documents
- Revision history
- Contact
NORA-B1 series - System integration manual
UBX-20027617 - R04 System description Page 14 of 61
C1-Public
The application core has one high-speed SPI controller (SPIM4) that can run at up to 32 Mbps. For
the fastest SPI mode, the pins shown in Table 4 must be used.
Signal
Pin name
Pin number
Direction
Pin drive setting
Description
SCK
P0.08
E2
O
H0H1
Serial clock, up to 32 MHz
MOSI
P0.09
C2
O
H0H1
Serial output data
MISO
P0.10
C1
I
H0H1
Serial input data
CSN
P0.11
B3
O
H0H1
Chip select, active low
DCX
P0.12
A2
O
H0H1
Data/command signal (optional)
Table 4: High-speed SPI dedicated pin assignments (SPIM4)
1.10.3 Quad Serial Peripheral Interface (QSPI)
To increase the memory size for application programs, external memory can be connected to
NORA-B1 module through the Quad Serial Peripheral port.
The QSPI is available through the application core and uses dedicated pins for the interface, as
shown in Table 5.
Signal
Pin name
Pin number
Direction
Pin drive setting
Description
IO0
P0.13
D2
I/O
H0H1
MOSI serial output data in single mode
Data I/O bit 0 in dual/quad mode
IO1
P0.14
E2
I/O
H0H1
MISO serial input data in single mode
Data I/O bit 1 in dual/quad mode
IO2
P0.15
D1
I/O
H0H1
Data I/O bit 2 in quad mode
IO3
P0.16
F2
I/O
H0H1
Data I/O bit 3 in quad mode
SCK
P0.17
F1
O
H0H1
Serial clock, up to 96 MHz
CSN
P0.18
E1
O
H0H1
Chip select, active low
Table 5: QSPI dedicated pin assignments
1.10.4 Inter-Integrated Circuit (I2C) interface
NORA-B1 supports up to five I2C ports that can operate in either controller or peripheral modes.
Four ports are available through the application core. One port is available through the network core.
The I2C interfaces can be used to transfer or receive data on a 2-wire bus network. NORA-B1 can
operate at 100 kbps (standard), 250 kbps, and 400 kbps (fast) transmission speeds. The interface
uses the SCL signal to clock instructions and transfers data on the SDA signal.
External pull-up resistors are required for the I2C interface. The value of the pull-up resistor should
be selected depending on the speed and capacitance of the bus. See Electrical specifications in the
NORA-B1 series data sheet [1] for recommended resistor values.
One of the application port I2C interfaces can be used in a high-speed mode at 1 Mbps. Dedicated
pins are required for this speed.
Signal
Pin name
Pin number
Direction
Pin drive setting
Description
SCL or SDA
P1.02
B4
I/0
E0E1
Either SCL or SDA may be assigned to this pin
SCL or SDA
P1.03
A3
I/O
E0E1
Either SCL or SDA may be assigned to this pin
Table 6: High-speed TWI dedicated pin assignments
☞ Set the pin drive to the S0D1 setting when assigning a I2C port to other pins.