Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Applications
- 1.3 Architecture
- 1.4 Pin assignments
- 1.5 Supply interfaces
- 1.6 System function interfaces
- 1.7 Debug
- 1.8 GPIO pins
- 1.9 Analog interfaces
- 1.10 Serial interfaces
- 1.10.1 Universal Asynchronous Receiver/Transmitter (UART)
- 1.10.2 Serial Peripheral Interface (SPI)
- 1.10.3 Quad Serial Peripheral Interface (QSPI)
- 1.10.4 Inter-Integrated Circuit (I2C) interface
- 1.10.5 Pulse Width Modulation (PWM) interface
- 1.10.6 Inter-IC Sound (I2S) interface
- 1.10.7 Pulse Density Modulation (PDM) interface
- 1.10.8 USB 2.0 device interface
- 1.11 Antenna interface
- 1.12 Reserved pins (RSVD)
- 1.13 GND pins
- 2 Software
- 3 Flashing application software
- 4 Design-in
- 5 Handling and soldering
- 6 Regulatory information and requirements
- 6.1 ETSI – European market
- 6.2 FCC/ISED – US/Canadian markets
- 6.3 MIC - Japanese market (pending)
- 6.4 NCC – Taiwanese market (pending)
- 6.5 KCC – South Korean market (pending)
- 6.6 ANATEL Brazil compliance (pending)
- 6.7 Australia and New Zealand regulatory compliance (pending)
- 6.8 South Africa regulatory compliance (pending)
- 6.9 Integration checklist
- 6.10 Pre-approved antennas list
- 7 Technology standards compliance
- 8 Product testing
- Appendix
- A Glossary
- B Antenna reference designs
- Related documents
- Revision history
- Contact
NORA-B1 series - System integration manual
UBX-20027617 - R04 System description Page 12 of 61
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1.9 Analog interfaces
Eight of the 48 digital GPIOs can be multiplexed with the following analog functions:
• 1x 8-channel ADC
• 1x analog comparator*
• 1x low-power analog comparator*
*Only one of the comparators can be used simultaneously.
1.9.1 ADC
The Analog-to-Digital Converter (ADC) can sample up to 200 kHz using different inputs as sample
triggers. Both one-shot conversion and continuous sampling are supported. Table 2 shows the
sample speed in correlation to the maximum source impedance. It supports 8/10/12-bit resolution.
The ADC includes 14-bit resolution if oversampling is used. Any of the eight analog inputs or VDD
can be used either as single-ended inputs or differential pairs for measuring the voltage between
them.
The ADC supports the full 0 V to VDD input range. If the sampled signal level is much lower than
VDD, it is possible to lower the input range of the ADC to encompass the desired signal and obtain a
higher effective resolution. Continuous sampling can be chosen for a configurable time interval, or
actively triggered for different internal or external events – with any CPU involvement.
Table 2: Acquisition versus source impedance
1.9.2 Comparator
The comparator compares voltages from any analog pin with different references, as shown in Table
3. It supports the full 0 V to VDD input range and can generate different software events to the rest
of the system. The comparator can operate in one of the following two modes:
• Single-ended Mode: A single reference level or an upper and lower hysteresis selectable from a
64-level reference ladder with a range from 0 V to VREF, as described in Table 3.
• Differential Mode: Two analog pin voltage levels are compared, optionally with a ~35 mV
hysteresis.
1.9.3 Low power comparator
The low-power comparator operates in the same way as the normal comparator, with reduced
functionality. It can be used during system OFF modes as a wake-up source.
ACQ [us]
Maximum source resistance [kΩ]
3
10
5
40
10
100
15
200
20
400
40
800