Integration Manual
Table Of Contents
- Document information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Applications
- 1.3 Architecture
- 1.4 Pin assignments
- 1.5 Supply interfaces
- 1.6 System function interfaces
- 1.7 Debug
- 1.8 GPIO pins
- 1.9 Analog interfaces
- 1.10 Serial interfaces
- 1.10.1 Universal Asynchronous Receiver/Transmitter (UART)
- 1.10.2 Serial Peripheral Interface (SPI)
- 1.10.3 Quad Serial Peripheral Interface (QSPI)
- 1.10.4 Inter-Integrated Circuit (I2C) interface
- 1.10.5 Pulse Width Modulation (PWM) interface
- 1.10.6 Inter-IC Sound (I2S) interface
- 1.10.7 Pulse Density Modulation (PDM) interface
- 1.10.8 USB 2.0 device interface
- 1.11 Antenna interface
- 1.12 Reserved pins (RSVD)
- 1.13 GND pins
- 2 Software
- 3 Flashing application software
- 4 Design-in
- 5 Handling and soldering
- 6 Regulatory information and requirements
- 6.1 ETSI – European market
- 6.2 FCC/ISED – US/Canadian markets
- 6.3 MIC - Japanese market (pending)
- 6.4 NCC – Taiwanese market (pending)
- 6.5 KCC – South Korean market (pending)
- 6.6 ANATEL Brazil compliance (pending)
- 6.7 Australia and New Zealand regulatory compliance (pending)
- 6.8 South Africa regulatory compliance (pending)
- 6.9 Integration checklist
- 6.10 Pre-approved antennas list
- 7 Technology standards compliance
- 8 Product testing
- Appendix
- A Glossary
- B Antenna reference designs
- Related documents
- Revision history
- Contact
NORA-B1 series - System integration manual
UBX-20027617 - R04 System description Page 11 of 61
C1-Public
1.6.2 Internal temperature sensor
The radio chip in the NORA-B1 contains a temperature sensor used to monitor the temperature of
the die.
⚠ The temperature sensor is located inside the radio chip and should not be used if an accurate
temperature reading of the surrounding environment is required.
1.7 Debug
1.7.1 Serial Wire Debug (SWD)
The primary interface for debugging is the SWD interface. NORA-B1 supports an SWD interface for
flashing and debugging. The two pins SWDIO and SWDCLK should be made accessible on header
pins or test points for production-line programming. Both cores use the same SWD interface.
1.8 GPIO pins
☞ The code running on the application core determines the pin mapping for both application
and network cores.
In an un-configured state, NORA-B1 has 48 GPIO pins and no analog or digital interfaces. All
interfaces or functions must be allocated to a GPIO pin before use. Eight of the 48 GPIO pins are
analog enabled, meaning that they can have an analog function allocated to them. Table 1 shows
the digital and analog functions that can be assigned to a GPIO pin.
Function
Description
Default
NORA-B1 pin
Configurable
GPIOs
General purpose input
Digital input with configurable pull-up, pull-down, edge detection
and interrupt generation
Any
General purpose output
Digital output with configurable drive strength, push-pull, or
open drain output
Any
Pin disabled
Pin is disconnected from the input and output buffers.
All
unconfigured
Any
Timer/ counter
High precision time measurement between two pulses/ pulse
counting with interrupt/event generation
Any
Interrupt/ Event trigger
Interrupt/event trigger to software application/ Wake-up event
Any
HIGH/LOW/Toggle on event
Programmable digital level triggered by internal or external
events without CPU involvement
Any
ADC input
8/10/12/14-bit analog to digital converter
Any analog
Analog comparator input
Compare two voltages, capable of generating wake-up events
and interrupts
Any analog
PWM output
Output simple or complex pulse width modulation waveforms
Any
Serial interfaces
For information about pin assignment restrictions, see Serial
interfaces.
Any
Table 1: GPIO custom functions configuration