Data Sheet

NINA-B40 series - Data sheet
UBX-19049405 - R04 Interfaces Page 17 of 40
C1 - Public
2.8.1 Drive strength
All GPIO pins are normally configured for lfow current consumption. Using this standard low-drive
strength, any pin configured as an output can only source or sink a certain amount of current. If the
timing requirements of any digital interface cannot be met, or if an LED requires more current than is
available in this mode, a high drive strength mode is available so the digital output can draw more
current. See section 4.2.8.
☞ Some GPIOs can introduce noise in the system when they are configured for high drive strength
or connected to a signal with a switching speed higher than 10 kHz. See the pinout in section 3.1
for more information.
2.9 Debug interfaces
2.9.1 SWD
NINA-B40 series modules provide a Serial Wire Debug (SWD) interface for flashing and debugging.
The SWD interface consists of two pins, SWDCLK and SWDIO.
2.9.2 Trace – Serial Wire Output
A serial trace option is available on the NINA-B40 series modules as an additional pin, SWO. The Serial
Wire Output (SWO) is used to:
 Support printf style debugging
 Trace OS and application events
 Emit diagnostic system information
A debugger that supports Serial Wire Viewer (SWV) is required.
2.9.3 Parallel Trace
The NINA-B40 series modules support parallel trace output as well. This allows output from the
Embedded Trace Macrocell (ETM) and Instrumentation Trace Macrocell (ITM) resources in the Arm®
Cortex®-M4 core of the nRF52833 chip in the NINA-B40. The ETM trace data allows a user to record
exactly how the application goes through the CPU instructions in real time. The parallel trace
interface uses 1 clock signal and 4 data signals respectively - TRACE_CLK, TRACE_D0, TRACE_D1,
TRACE_D2 and TRACE_D3.