Data Sheet

NINA-B40 series - Data sheet
UBX-19049405 - R04 Interfaces Page 13 of 40
C1 - Public
o 1 stop bit
 Default frame configuration is 8N1, meaning eight (8) data bits, no (N) parity bit, and one (1) stop
bit.
 Frames are transmitted in such a way that the least significant bit (LSB) is transmitted first.
2.5.2 Serial peripheral interface (SPI)
NINA-B40 supports up to four Serial Peripheral Interfaces with serial clock frequencies of up to 32
MHz. Characteristics of the SPI interfaces are listed below:
 Pin configuration in master mode:
o SCLK, Serial clock output, up to 32 MHz
o MOSI, Master Output Slave Input data line
o MISO, Master Input Slave Output data line
o CS, Chip/Slave select output, active low, selects which slave on the bus to talk to. Only one
select line is enabled by default but more can be added by customizing a GPIO pin.
o DCX, Data/Command signal, this signal is optional but is sometimes used by the SPI slaves to
distinguish between SPI commands and data
 Pin configuration in slave mode:
o SCLK, Serial clock input
o MOSI, Master Output Slave Input data line
o MISO, Master Input Slave Output data line
o CS, Chip/Slave select input, active low, connects/disconnects the slave interface from the bus.
 Both master and slave modes are supported on all the interfaces.
 The serial clock supports both normal and inverted clock polarity (CPOL) and data should be
captured on rising or falling clock edge (CPHA).
2.5.3 Inter-Integrated Circuit interface (I2C)
The Inter-Integrated Circuit (I2C) interfaces can be used to transfer and/or receive data on a 2-wire
bus network. The NINA-B40 modules can operate as both master and slave on the I2C bus using
standard (100 kbps), fast (400 kbps), and 250 kbps transmission speeds. The interface supports
clock stretching, which allows NINA-B40 to temporarily pause any I2C communications. Up to 127
individually addressable I2C devices can be connected to the same two signals.
 Pin configuration:
o SCL, clock output in master mode, input in slave mode
o SDA, data input/output pin
This interface requires external pull-up resistors to work properly in the master mode; see section
4.2.9 for suggested resistor values. The pull-up resistors are also required in slave mode and these
should be placed at the master end of the interface.
2.5.4 Inter-IC Sound interface (I2S)
The Inter-IC Sound (I2S) interface can be used to transfer audio sample streams between NINA-B40
and external audio devices such as codecs, DACs, and ADCs. It supports original I2S and left or right-
aligned interface formats in both master and slave modes.
 Pin configuration:
o MCK, master clock
o LRCK, left right/word/sample clock
o SCK, serial clock
o SDIN, serial data in
o SDOUT, serial data out