User's Manual

NINA-B1 series - Data Sheet
UBX-15019243 - R05 Early Production Information Interfaces
Page 11 of 35
 Low level on the RESET_N input pin, normally high with internal pull-up. This causes an “external” or
“hardware” reset of the module. The current parameter settings are not saved in the module’s
non-volatile memory and a proper network detach is not performed.
 Using the AT+CPWROFF command. This causes an “internal” or “software” reset of the module. The
current parameter settings are saved in the module’s non-volatile memory and a proper network detach
is performed.
2.3.6 Real Time Counter (RTC)
A key system feature available on the module is the Real Time Counter. This counter can generate multiple
interrupts and events to the CPU and radio as well as internal and external hardware blocks. These events can be
precisely timed ranging from microseconds up to hours, and allows for periodic BLE advertising events etc.,
without involving the main CPU. The RTC can be operated in power-on and standby modes.
2.4 Serial interfaces
NINA-B1 modules provide the following serial communication interfaces:
 1x UART interface: 4-wire unbalanced asynchronous serial interface used for AT commands interface,
data communication and firmware upgrades using the FOAT feature.
 3x SPI interfaces: Up to three serial peripheral interfaces can be used simultaneously.
 2x I2C interfaces: Inter-Integrated Circuit (I2C) interface for communication with digital sensors.
All digital interface pins on the module are shared between the digital and analog interfaces and GPIOs.
Any function can be assigned to any pin that is not already occupied.
2.4.1 Asynchronous serial interface (UART)
The UART interface supports hardware flow control and baud-rates up to 1 Mbps. Other characteristics of the
UART interface are listed below:
 Data lines (RXD as input, TXD as output) and hardware flow control lines (CTS as input, RTS as output)
are provided.
 Hardware flow control or no flow control (default) is supported.
 Power saving indication available on the hardware flow control output (CTS line): The line is driven to
the OFF state when the module is not ready to accept data signals.
 Programmable baud-rate generator allows most industry standard rates, as well as non-standard rates
up to 1 Mbps.
 Frame format configuration:
o 8 data bits
o Even or no-parity bit
o 1 stop bit
 Default frame configuration is 8N1, meaning eight (8) data bits, no (N) parity bit, and one (1) stop bit.
2.4.2 Serial peripheral interface (SPI)
NINA-B1 supports up to 3 Serial Peripheral Interfaces that can operate in both master and slave mode with a
maximum serial clock frequency of 8 MHz in both master and slave modes. The SPI interfaces use 4 signals:
SCLK, MOSI, MISO and CS. When using the SPI interface in master mode, it is possible to use GPIOs as
additional Chip Select (CS) signals to allow addressing of multiple slaves.
2.4.3 I
2
C interface
The Inter-Integrated Circuit interfaces can be used to transfer or receive data on a 2-wire bus network. The
NINA-B1 modules can operate as both master and slave on the I
2
C bus using both standard (100 kbps) and fast
(400 kbps) transmission speeds. The interface uses the SCL signal to clock instructions and data on the SDL
signal.