Integration Manual
Table Of Contents
- Document Information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Power management
- 1.6 System functions
- 1.7 RF connection
- 1.8 (U)SIM interface
- 1.9 Serial communication
- 1.9.1 Serial interfaces configuration
- 1.9.2 Asynchronous serial interface (UART)
- 1.9.2.1 UART features
- 1.9.2.2 UART signal behavior
- 1.9.2.3 UART and power-saving
- 1.9.2.4 UART application circuits
- Providing the full RS-232 functionality (using the complete V.24 link)
- Providing the TxD, RxD, RTS, CTS and DTR lines only (not using the complete V.24 link)
- Providing the TxD, RxD, RTS and CTS lines only (not using the complete V.24 link)
- Providing the TxD and RxD lines only (not using the complete V24 link)
- Additional considerations
- 1.9.3 USB interface
- 1.9.4 SPI interface
- 1.9.5 MUX protocol (3GPP TS 27.010)
- 1.10 DDC (I2C) interface
- 1.11 Audio Interface
- 1.12 General Purpose Input/Output (GPIO)
- 1.13 Reserved pins (RSVD)
- 1.14 Schematic for LISA-U2 module integration
- 1.15 Approvals
- 1.15.1 European Conformance CE mark
- 1.15.2 US Federal Communications Commission notice
- 1.15.3 Innovation, Science, Economic Development Canada notice
- 1.15.4 Australian Regulatory Compliance Mark
- 1.15.5 ICASA Certification
- 1.15.6 KCC Certification
- 1.15.7 ANATEL Certification
- 1.15.8 CCC Certification
- 1.15.9 Giteki Certification
- 2 Design-In
- 3 Features description
- 3.1 Network indication
- 3.2 Antenna detection
- 3.3 Jamming Detection
- 3.4 TCP/IP and UDP/IP
- 3.5 FTP
- 3.6 HTTP
- 3.7 SSL/TLS
- 3.8 Dual stack IPv4/IPv6
- 3.9 AssistNow clients and GNSS integration
- 3.10 Hybrid positioning and CellLocate®
- 3.11 Control Plane Aiding / Location Services (LCS)
- 3.12 Firmware update Over AT (FOAT)
- 3.13 Firmware update Over the Air (FOTA)
- 3.14 In-Band modem (eCall / ERA-GLONASS)
- 3.15 SIM Access Profile (SAP)
- 3.16 Smart Temperature Management
- 3.17 Bearer Independent Protocol
- 3.18 Multi-Level Precedence and Pre-emption Service
- 3.19 Network Friendly Mode
- 3.20 Power saving
- 4 Handling and soldering
- 5 Product Testing
- Appendix
- A Migration from LISA-U1 to LISA-U2 series
- A.1 Checklist for migration
- A.2 Software migration
- A.2.1 Software migration from LISA-U1 series to LISA-U2 series modules
- A.3 Hardware migration
- A.3.1 Hardware migration from LISA-U1 series to LISA-U2 series modules
- A.3.2 Pin-out comparison LISA-U1 series vs. LISA-U2 series
- A.3.3 Layout comparison LISA-U1 series vs. LISA-U2 series
- B Glossary
- Related documents
- Revision history
- Contact
LISA-U2 series - System Integration Manual
UBX-13001118 - R25 System description Page 91 of 182
Connection with u-blox 3.0 V GNSS receivers
Figure 48 shows an application circuit for connecting a LISA-U2 cellular module to a u-blox 3.0 V GNSS
receiver:
As the SDA and SCL pins of the LISA-U2 cellular module are not tolerant up to 3.0 V, the
connection to the related I
2
C pins of the u-blox 3.0 V GNSS receiver must be provided using a
proper I
2
C-bus Bidirectional Voltage Translator (e.g. TI TCA9406, which additionally provides the
partial power down feature so that the GNSS 3.0 V supply can be ramped up before the V_INT 1.8
V cellular supply), with proper pull-up resistors.
As the GPIO3 and GPIO4 pins of the LISA-U2 cellular module are not tolerant up to 3.0 V, the
connection to the related pins of the u-blox 3.0 V GNSS receiver must be provided using a proper
Unidirectional General Purpose Voltage Translator (e.g. TI SN74AVC2T245, which additionally
provides the partial power down feature so that the 3.0 V GNSS supply can be also ramped up
before the V_INT 1.8 V cellular supply).
The V_BCKP supply output of the cellular module can be directly connected to the V_BCKP backup
supply input pin of the GNSS receiver as in the application circuit for a u-blox 1.8 V GNSS receiver.
LISA-U2 series
u-blox GNSS
3.0 V receiver
23
GPIO3
24
GPIO4
1V8
B1 A1
GND
U3
B2A2
VCCBVCCA
Unidirectional
Voltage Translator
C4
C5
3V0
TxD1
EXTINT0
R1
INOUT
GND
GPS LDO
Regulator
SHDN
R2
VMAIN3V0
U1
21
GPIO2
46
SDA
45
SCL
R4 R5
1V8
SDA_A SDA_B
GND
U2
SCL_ASCL_B
VCCA
VCCB
I2C-bus Bidirectional
Voltage Translator
4
V_INT
C1
C2
C3
R3
SDA2
SCL2
VCC
DIR1
DIR2
2
V_BCKPV_BCKP
OE
R7
OE
Figure 48: DDC Application circuit for a u-blox 3.0 V GNSS receiver
Reference
Description
Part Number - Manufacturer
R1, R2, R4, R5, R7
4.7 kΩ Resistor 0402 5% 0.1 W
RC0402JR-074K7L - Yageo Phycomp
R3
47 kΩ Resistor 0402 5% 0.1 W
RC0402JR-0747KL - Yageo Phycomp
C2, C3, C4, C5
100 nF Capacitor Ceramic X5R 0402 10% 10V
GRM155R71C104KA01 - Murata
U1, C1
Voltage Regulator for GNSS receiver and
related output bypass capacitor
See GNSS receiver Hardware Integration Manual
U2
I2C-bus Bidirectional Voltage Translator
TCA9406DCUR - Texas Instruments
U3
Generic Unidirectional Voltage Translator
SN74AVC2T245 - Texas Instruments
Table 39: Components for DDC application circuit for a u-blox 3.0 V GNSS receiver