Integration Manual

LISA-U2 series - System Integration Manual
UBX-13001118 - R25 System description Page 84 of 182
4
V_INT
MOSI
Application processor
(3.0V SPI master)
MISO
SCLK
Interrupt
GND
LISA-U2 series
(1.8V SPI slave)
56
SPI_MOSI
57
SPI_MISO
55
SPI_SCLK
58
SPI_SRDY
GND
U1
VCC
GPIO
GPIO
59
SPI_MRDY
1V8
B1 A1
GND
U1
B3A3
VCCBVCCA
Unidirectional
Voltage Translator
C1
C2
3V0
DIR3
DIR2
OE
DIR1
B2 A2
B4A4
DIR4
1V8
B1 A1
GND
U2
VCCBVCCA
Unidirectional
Voltage Translator
C3
C4
3V0
DIR2
DIR1
OE
B2 A2
Figure 46: IPC / SPI Interface application circuit connecting LISA-U2 series 1.8V SPI slave to a 3.0 V SPI master
Reference
Description
Part Number - Manufacturer
C1, C2, C3, C4
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R61A104KA01 - Murata
U1
Unidirectional Voltage Translator
SN74AVC4T774 - Texas Instruments
U2
Unidirectional Voltage Translator
SN74AVC2T245 - Texas Instruments
Table 36: Parts for IPC / SPI Interface application circuit connecting LISA-U2 series 1.8V SPI slave to a 3.0 V SPI master
☞ If the SPI/IPC interface is not used, the SPI_MOSI, SPI_MISO, SPI_SCLK, SPI_MRDY, SPI_SRDY
pins can be left unconnected.
☞ Any external signal connected to the SPI / IPC interface must be tri-stated when the module is in
power-down mode, when the external reset is forced low and during the module power-on
sequence (at least for 3 seconds after the start-up event), to avoid latch-up of circuits and allow a
clean boot of the module. If the external signals connected to the cellular module cannot be tri-
stated, insert a multi-channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159,
or TS5A63157) between the two circuit connections and set to high impedance during module
power-down mode, when external reset is forced low, and during the power-on sequence.
1.9.5 MUX protocol (3GPP TS 27.010)
LISA-U2 modules have a software layer with MUX functionality, as peer the 3GPP TS 27.010
Multiplexer Protocol [6], available either on the UART or on the SPI physical link. The USB interface
does not support the multiplexer protocol.
This is a data link protocol (layer 2 of OSI model) which uses HDLC-like framing and operates between
the module (DCE) and the application processor (DTE) and allows a number of simultaneous sessions
over the used physical link (UART or SPI): the user can concurrently use the AT command interface on
one MUX channel and Packet-Switched / Circuit-Switched data communication on another MUX
channel. The multiplexer protocol can be used on one serial interface (UART or SPI) at a time. Each
session consists of a stream of bytes transferring various kinds of data such as SMS, CBS, PSD,
GNSS, and AT commands in general. This permits, for example, SMS to be transferred to the DTE
when a data connection is in progress.