Integration Manual

LISA-U2 series - System Integration Manual
UBX-13001118 - R25 System description Page 83 of 182
1.9.4.4 IPC application circuits
SPI_MOSI is the data line input for the module since it runs as an SPI slave: it must be connected to
the data line output (MOSI) of the application processor that runs as an SPI master.
SPI_MISO is the data line output for the module since it runs as an SPI slave: it must be connected to
the data line input (MISO) of the application processor that runs as an SPI master.
SPI_SCLK is the clock input for the module since it runs as an SPI slave: it must be connected to the
clock line output (SCLK) of the application processor that runs as an SPI master.
SPI_MRDY is an input for the module able to detect an external interrupt which comes from the SPI
master: it must be connected to a GPIO of the application processor that runs as an SPI master.
SPI_SRDY is an output for the module that must be connected to a pin of the application processor
that runs as an SPI master able to detect an external interrupt which comes from the module.
Signal integrity of the high speed data lines may be degraded if the PCB layout is not optimal,
especially when the SPI lines are very long: keep routing short and minimize parasitic capacitance to
preserve signal integrity. It is recommended to match the length of SPI signals.
If a 1.8 V application processor is used, the SPI master pins can be directly connected to the specific
LISA-U2 SPI slave pins as described in Figure 45. It is recommended to tri-state the output pins of the
SPI Master (i.e. set in high impedance mode) when the LISA-U2 module is in power-down mode, when
the external reset is forced low, and during the module power-on sequence (at least for 3 seconds
after the start-up event), to avoid latch-up of circuits and allow a clean boot of the module.
MOSI
Application processor
(1.8V SPI master)
MISO
SCLK
Interrupt
GND
LISA-U2 series
(1.8V SPI slave)
56
SPI_MOSI
59
SPI_MRDY
57
SPI_MISO
55
SPI_SCLK
58
SPI_SRDY
GND
GPIO
Figure 45: IPC / SPI Interface application circuit connecting LISA-U2 series 1.8V SPI slave to a 1.8V SPI master
If a 3.0 V SPI master application processor is used, implement a circuit with appropriate unidirectional
voltage translators with tri-state (i.e. high impedance) mode controlled by the application processor,
as illustrated in Figure 46.