Integration Manual

LISA-U2 series - System Integration Manual
UBX-13001118 - R25 System description Page 82 of 182
Master-initiated transfer with a sleeping slave
Figure 43: Data transfer initiated by the application processor (master) with a sleeping LISA-U2 module (slave)
When the slave is sleeping (idle mode), the following actions happen:
1. The master wakes the slave by setting the SPI_MRDY line active.
2. As soon as the slave is awake, it signals it by activating SPI_SRDY.
3. The master activates the clock and the two processors exchange the communication header and
data.
4. If the data has been exchanged, the slave deactivates SPI_SRDY to process the received
information. The master does not need to de-assert SPI_MRDY as it controls the SPI_SCLK.
5. After the preparation, the slave activates SPI_SRDY again and waits for SPI_SCLK activation.
When the clock is active, all data is transferred without intervention. If there is more data to
transfer (flag set in any of the headers), the process will repeat from step 3.
Slave ended transfer
Figure 44: Data transfer terminated and then restarted by LISA-U2 module (slave)
Starting from the state where data transfer is ongoing, the following actions will happen:
1. In case of the last transfer, the master will lower its SPI_MRDY line. After the data transfer is
finished, the line must be low. If the slave has already set its SPI_SRDY line, the master must
raise its line to initiate the next transfer (slave-waking-procedure).
2. If the data has been exchanged, the slave will deactivate SPI_SRDY to process the received
information. This is the normal behavior.
3. The slave will indicate the master that is ready to send data by activating SPI_SRDY.
4. When the master is ready to send, it will signalize this by activating SPI_MRDY. This is optional,
when SPI_MRDY is low before.
5. The slave indicates immediately after a transfer termination that it is ready to start transmission
again. In this case, the slave will raise SPI_SRDY again. The SPI_MRDY line can be either high or
low: the master only needs to ensure that the SPI_SRDY change will be detected correctly via
interrupt.
☞ For more details regarding IPC communication protocol, see the SPI Application Note [17].
SPI_MRDY
SPI_SRDY
DATA EXCHG
1
2
4
5
Header
Data
Header
3
SPI_MRDY
SPI_SRDY
DATA EXCHG
5
2
1
Header
Data
3
4