Integration Manual

LISA-U2 series - System Integration Manual
UBX-13001118 - R25 System description Page 81 of 182
1.9.4.2 IPC communication and power saving
If power saving is enabled by an AT command (AT+UPSV=1, AT+UPSV=2 or AT+UPSV=3), the LISA-
U2 module automatically enters idle mode whenever possible, if the master indicates that it is not
ready to transmit or receive by the SPI_MRDY signal, or if the LISA-U2 series module itself does not
transfer data.
1.9.4.3 IPC communication examples
In the following, three IPC communication scenarios are described:
 Slave-initiated data transfer, with a sleeping master
 Master-initiated data transfer, with a sleeping slave
 Slave-ended data transfer
Slave-initiated transfer with a sleeping master
Figure 42: Data transfer initiated by the LISA-U2 module (slave), with a sleeping application processor (master)
When the master is sleeping (idle mode), the following actions happen:
1. The slave indicates to the master that is ready to send data by activating SPI_SRDY.
2. When the master becomes ready to send, it signalizes this by activating SPI_MRDY.
3. The master activates the clock and the two processors exchange the communication header and
data.
4. If the data has been exchanged, the slave deactivates SPI_SRDY to process the received
information. The master does not need to de-assert SPI_MRDY as it controls the SPI_SCLK.
5. After the preparation, the slave activates SPI_SRDY again and waits for SPI_SCLK activation.
When the clock is active, all the data is transferred without intervention. If there is more data to
transfer (flag set in any of the headers), the process will repeat from step 3.
SPI_MRDY
SPI_SRDY
DATA EXCHG
2
4
5
Header
Data
Header
3
1