Integration Manual

LISA-U2 series - System Integration Manual
UBX-13001118 - R25 System description Page 79 of 182
1.9.4 SPI interface
SPI is a master-slave protocol: the module runs as an SPI slave, i.e. it accepts AT commands on its SPI
interface without any specific configuration. The SPI-compatible synchronous serial interface cannot
be used for the FW upgrade.
The standard 3-wire SPI interface includes two signals to transmit and receive data (SPI_MOSI and
SPI_MISO) and a clock signal (SPI_SCLK).
LISA-U2 modules provide two handshake signals (SPI_MRDY and SPI_SRDY), added to the standard
3-wire SPI interface, implementing the 5-wire Inter Processor Communication (IPC) interface.
The purpose of the IPC interface is to achieve high speed communication (up to 26 Mbit/s) between
two processors following the same IPC specifications: the module baseband processor and an
external processor. High speed communication is possible only if both sides follow the same Inter
Processor Communication (IPC) specifications.
The module firmware can be upgraded over the SPI interface by means of an AT command (for more
details, see section 3.1 and the Firmware Update application note [16]).
Name
Description
Remarks
SPI_MISO
SPI Data Line.
Master Input, Slave Output
Module Output.
Idle high.
Shift data on rising clock edge (CPHA=1).
Latch data on falling clock edge (CPHA=1).
MSB is shifted first.
SPI_MOSI
SPI Data Line.
Master Output, Slave Input
Module Input.
Idle high.
Shift data on rising clock edge (CPHA=1).
Latch data on falling clock edge (CPHA=1).
MSB is shifted first.
Internal active pull-up to V_INT (1.8 V) enabled.
SPI_SCLK
SPI Serial Clock.
Master Output, Slave Input
Module Input.
Idle low (CPOL=0).
Supported clock frequency: from 260 kHz up to 26 MHz.
Internal active pull-down to GND enabled.
SPI_MRDY
SPI Master Ready to transfer data control line.
Master Output, Slave Input
Module Input.
Idle low.
Internal active pull-down to GND enabled.
SPI_SRDY
SPI Slave Ready to transfer data control line.
Master Input, Slave Output
Module Output.
Idle low.
Table 35: SPI interface signals
☞ The SPI interface pins’ ESD sensitivity rating is 1 kV (Human Body Model according to
JESD22-A114F). Higher protection levels could be required if the lines are externally accessible on
the application board. Higher protection levels can be achieved by mounting a low capacitance (i.e.
less than 10 pF) ESD protection (e.g. AVX USB0002 varistor array) on the lines connected to these
pins, close to the accessible points.