Integration Manual

LISA-U2 series - System Integration Manual
UBX-13001118 - R25 System description Page 70 of 182
If only the TxD, RxD, RTS, CTS and DTR lines are provided (as implemented in Figure 33 and in Figure
34) and if HW flow-control is enabled (AT&K3, default setting), the power saving can be activated as
it can be done when the complete UART link is provided (9-wire, as implemented in Figure 31 and in
Figure 32), i.e. in these ways:
 AT+UPSV=1: the module automatically enters the low-power idle mode whenever possible and the
UART interface is periodically enabled, as described in section 1.9.2.3, reaching low current
consumption.
With this configuration, when the module is in idle mode, the data transmitted by the DTE will be
buffered by the DTE and will be correctly received by the module when active mode is entered.
 AT+UPSV=3: the module automatically enters the low-power idle mode whenever possible and the
UART interface is enabled by the DTR line, as described in section 1.9.2.3, reaching very low current
consumption.
With this configuration, not supported by the “01” product version, when the module is in idle
mode, the UART is re-enabled 20 ms after DTR has been set ON, and the recognition of
subsequent characters is guaranteed until the module is in active mode
If the HW flow-control is disabled (AT&K0), it is recommended to enable the power saving in one of
these ways:
 AT+UPSV=2: the module automatically enters the low-power idle mode whenever possible and the
UART interface is enabled by the RTS line, as described in section 1.9.2.3, reaching very low current
consumption.
With this configuration, when the module is in idle mode, the UART is re-enabled 20 ms after RTS
has been set ON, and the recognition of subsequent characters is guaranteed until the module is
in active mode.
 AT+UPSV=3: the module automatically enters the low-power idle mode whenever possible and the
UART interface is enabled by the DTR line, as described in section 1.9.2.3, reaching very low current
consumption.
With this configuration, not supported by the “01” product version, when the module is in idle
mode, the UART is re-enabled 20 ms after DTR has been set ON, and the recognition of
subsequent characters is guaranteed until the module is in active mode.
Providing the TxD, RxD, RTS and CTS lines only (not using the complete V.24 link)
If the functionality of the DSR, DCD, RI and DTR lines is not required, or the lines are not available:
 Connect the module DTR input line to GND, to robustly fix the logic level
 Leave the DSR, DCD and RI lines of the module unconnected and floating
If RS-232 compatible signal levels are needed, the Maxim 13234E voltage level translator can be used.
This chip translates voltage levels from 1.8 V (module side) to the RS-232 standard.
Figure 35 describes the circuit that should be implemented as if a 1.8 V application processor is used.
TxD
Application processor
(1.8V DTE)
RxD
RTS
CTS
DTR
DSR
RI
DCD
GND
LISA-U2 series
(1.8V DCE)
15
TXD
12
DTR
16
RXD
13
RTS
14
CTS
9
DSR
10
RI
11
DCD
GND
0 Ω
0 Ω
TP
TP
0 Ω
0 Ω
TP
TP
Figure 35: UART interface application circuit with partial V.24 link (5-wire) in the DTE/DCE serial communication (1.8 V DTE)