Integration Manual

LISA-U2 series - System Integration Manual
UBX-13001118 - R25 System description Page 65 of 182
AT+UPSV=3: power saving enabled and controlled by the DTR line
The AT+UPSV=3 configuration can be enabled regardless of the flow control setting on UART. In
particular, the HW flow control can be enabled (AT&K3) or disabled (AT&K0) on UART during this
configuration.
The UART interface is immediately disabled after the DTE sets the DTR line to OFF.
Then the module automatically enters idle mode whenever possible according to any required activity
related to the network or any other required activity related to the functions / interfaces of the module.
The UART is disabled as long as the DTR line is set to OFF, but the UART is enabled in case the module
needs to transmit some data over the UART (e.g. URC).
When an OFF-to-ON transition occurs on the DTR input line, the UART is re-enabled and the module,
if it was in idle mode, switches from idle to active mode after 20 ms: this is the UART and module
“wake-up time”.
If the DTR line is set to ON by the DTE, the module is not allowed to enter idle mode and the UART is
kept enabled until the DTR line is set to OFF.
When the AT+UPSV=3 configuration is enabled, the DTR input line can still be used by the DTE to
control the module behavior according to AT&D command configuration (see u-blox AT Commands
Manual [2]).
☞ The CTS output line indicates the UART power saving state as illustrated in Figure 28, if HW flow
control is enabled with AT+UPSV=3.
☞ The AT+UPSV=3 power saving configuration is not supported by the “01” product version.
Wake-up via data reception
The UART wake-up via data reception consists of a special configuration of the module TXD input line
that causes the system wake-up when a low-to-high transition occurs on the TXD input line. In
particular, the UART is enabled and the module switches from the low-power idle mode to active mode
within ~20 ms from the first character received: this is the system “wake-up time”.
As a consequence, the first character sent by the DTE when the UART is disabled (i.e. the wake-up
character) is not a valid communication character even if the wake-up via data reception configuration
is active, because it cannot be recognized, and the recognition of the subsequent characters is
guaranteed only after the complete system wake-up (i.e. after ~20 ms).
The UART wake-up via data reception configuration is active in the following case:
 the TXD input line is configured to wake up the system via data reception only if AT+UPSV=1 is set
with hardware flow control disabled
The UART wake-up via data reception configuration is not active on the TXD input, and therefore all
the data sent by the DTE is lost, if:
 AT+UPSV=2 is set with HW flow control disabled, and the RTS line is set OFF
 AT+UPSV=3 is set, regardless of the HW flow control setting, and the DTR line is set OFF
Figure 29 and Figure 30 show examples of common scenarios and timing constraints:
 AT+UPSV=1 power saving configuration is active and the timeout from last data received to idle
mode start is set to 2000 frames (AT+UPSV=1,2000)
 Hardware flow control is disabled